DLA SMD-5962-89698 REV B-2013 MICROCIRCUIT LINEAR A D CONVETER 10-BIT SAMPLING MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Drawing updated to reflect current requirements. - lgt 01-10-02 Raymond Monnin B Redrawn. Paragraphs updated to MIL-PRF-38535 requirements. - drw 13-03-05 Charles F. Saffle THE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED. REV SHEET REV

2、 B B SHEET 15 16 REV STATUS REV B B B B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Rick C. Officer DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL D

3、EPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE CHECKED BY Charles E. Besore APPROVED BY Michael A. Frye MICROCIRCUIT, LINEAR, A/D CONVETER, 10-BIT SAMPLING, MONOLITHIC SILICON DRAWING APPROVAL DATE 90-02-26 AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 67268 5962-89698 SHEET 1 OF 16 DSCC FORM 223

4、3 APR 97 5962-E303-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89698 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing desc

5、ribes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-89698 01 L A Drawing number Device type (see 1.2.1) Case outline (s

6、ee 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device types. The device types identify the circuit function as follows: Device type Generic number Circuit function 01 AD7579 10-bit A/D converter with an (8+2) read interfacing structure 02 AD7580 10-bit A/D converter with a 10-bit parallel word 1.2.2 Case o

7、utline. The case outline is as designated in MIL-STD-1835 as follows: Outline letter Descriptive designator Terminals Package style L GDIP3-T24 or CDIP4-T24 24 Dual-in-line 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. VDDto AGND, DGND

8、 -0.3 V dc to +7.0 V dc AGND to DGND -0.3 V dc to VDDDigital input voltage to DGND . -0.3 V dc to VDD+0.3 V dc Digital output voltage to DGND . -0.3 V dc to VDD+0.3 V dc CLK input voltage to DGND -0.3 V dc to VDD+0.3 V dc VREFto AGND -0.3 V dc to VDDVIN()A, VIN()B to AGND (see figure 1) -0.3 V dc to

9、 VDD+0.3 V dc VIN()A to AGND (see figure 2) . -0.6 V dc to 2VDD+0.6 V dc VIN()A to AGND (see figure 3) . VDD 0.3 V dc to VDD+ 0.3 V dc Storage temperature range . -65C to +150C Lead temperature (soldering, 10 seconds) +300C Power dissipation at TA 75C (PD) 1/ 450 mW Thermal resistance, junction to c

10、ase (JC). See MIL-STD-1835 Junction temperature (TJ) +175C _ 1/ Derate above TA= +75C at 6.0 mW/C. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89698 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISIO

11、N LEVEL B SHEET 3 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions. Supply voltage range (VDD) . +4.75 V dc to +5.25 V dc Reference voltage (VREF) +2.5 V Analog and digital ground voltage (AGND and DGND) . 0 V Clock frequency (fCLK) . 2.5 MHz Analog input range (see figure 1) : Span VREFCo

12、mmon mode range 0 V to VDDAnalog input range (see figure 2) : Span 2VREFCommon mode range 0 V to 2VDDAnalog input range (see figure 3) : Span 2VREFCommon mode range -VREFto (2VDD- VREF) Ambient operating temperature range (TA) . -55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, sta

13、ndards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Inte

14、grated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MI

15、L-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict betwe

16、en the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. Provided by IHSNot for ResaleNo reproduction or networking permitted wi

17、thout license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89698 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for

18、non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in a

19、ccordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of

20、the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensi

21、ons shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outline. The case outline shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth tables. The truth tables shall be as specified on figu

22、re 2. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full ambient operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be t

23、he subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For pack

24、ages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38

25、535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed

26、 as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DLA Land and Maritime -VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirement

27、s herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DLA Land and Maritime -VA shall be required for any change

28、 that affects this drawing. 3.9 Verification and review. DLA Land and Maritime, DLA Land and Maritimes agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option

29、of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89698 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteri

30、stics. Test Symbol Conditions 1/ -55C TA+125C unless otherwise specified Group A subgroups Device type Limits Unit Min Max Integral nonlinearity 2/ INL All 1, 2, 3 1.0 LSB Differential nonlinearity 2/ DNL No missing codes guaranteed over the full temperature range All 1, 2, 3 0.9 LSB Full scale erro

31、r 2/ AE All 1, 2, 3 5.0 LSB Zero code error 2/, 3/ AZCEConnected as on figure 3 All 1, 2, 3 3.0 LSB Connected as on figure 4 3.0 Power supply rejection 4/ PSR 4.75 V VDD 5.25 V All 1, 2, 3 0.5 LSB Power supply current IDDVDD= +5.0 V All 1, 2, 3 10 mA Attenuator input 5/ resistance RIN(AT)All 1, 2, 3

32、 5.0 15 M Comparator input resistance RIN(COMP)Connected as on figure 3 All 1, 2, 3 10 M Reference input current IREFALL 1, 2, 3 10 M Digital input low voltage VINLCS , RD , WR , HBEN and CLK, HBEN, device 01 only All 1, 2, 3 0.8 V Digital input high voltage VINH2.4 Digital input current IINCS , RD

33、, WR , HBEN, and CLK, VIN= 0 V to VDD HBEN, device 01 only All 1 1.0 A 2, 3 10 Input capacitance 6/ CINCS , RD , WR , HBEN, and CLK, see 4.3.1c, TA= +25C HBEN, device 01 only All 4 10 pF Digital output low voltage VOLDB0 to DB7, ISINK= 1.6 mA All 1, 2, 3 0.4 V Digital output high voltage VOHDB0 to D

34、B7, ISOURCE= 400 A All 1, 2, 3 4.0 V Floating state leakage current ILGDB0 DB7, VOUT= 0 to VDDAll 1, 2, 3 10.0 A Floating state output 6/ capacitance COUTDB0 DB7, see 4.3.1c, TA= +25C All 4 10 pF Output low voltage VOLRDY, INT, ISINK= 1.6 mA All 1, 2, 3 0.4 V Conversion time 7/ TCONVfCLK= 2.5 MHz, t

35、WR= 100 s All 1, 2, 3 16.9 18.5 s See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89698 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 A

36、PR 97 TABLE I. Electrical performance characteristics - continued. Test Symbol Conditions 1/ -55C TA+125C unless otherwise specified Group A subgroups Device type Limits Unit Min Max Sampling rate 7/ tSAMPAll 7, 8 50 kHz Functional test See 4.3.1b All 7, 8 Signal-to-noise ratio 6/, 7/ SNR All 4, 5,

37、6 55 dB CS to WR setup time 6/ t1See figure 6 8/ All 9, 10, 11 0 ns WR pulse width t29 40 10, 11 50 CS to WR hold time 6/ t39, 10, 11 0 WR to INT propagation delay time 6/ t4See figures 6, 8, and 9 9/ All 9 100 ns 10, 11 120 CS to RD setup time 6/ t5See figure 7 8/ All 9, 10, 11 0 ns RD pulse width

38、6/ t6All 9, 10, 11 t12CS to RD hold time 6/ t7All 9, 10, 11 0 HBEN to RD setup time t801 9 20 10, 11 30 HBEN to RD hold time t901 9, 10, 11 10 RDY access time 6/ t10See figures 7, 8, and 9 9/ All 9 110 ns 10, 11 150 RD to INT propagation delay time 6/ t11All 9 100 10, 11 120 Data access time after R

39、D t12All 9 110 10, 11 150 Data hold time, RDY hold time t13See figures 7 and 10 6/, 10/ All 9 10 65 ns 10, 11 10 90 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89698 DLA LAN

40、D AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - continued. 1/ VDD= +5.0 V 5.0 %, VREF= +2.5 V, AGND = DGND = 0 V, fCLK= 2.5 MHz, and connected as shown on figure 3, unless otherwise specified. 2/ Specifications

41、 applies for the three Analog Input Ranges: 0 to VDD, 0 to 2VDD, -VREFto (2VDD- VREF). INL tested using figure 3, DNL tested using figure 4, configuration B. 3/ Zero code error is measured with respect to an ideal first code transition which occurs at 0.5 LSB. 4/ Power supply rejection is tested for

42、 full scale error only. 5/ Resistance is measured between VIN(+)A, VIN(+)B or VIN(-)A, VIN(-)B. 6/ Measured only for the initial test and after any process or design changes which may affect these parameters. 7/ These specifications apply for full scale input signals up to 20 kHz. 8/ All input contr

43、ol signals are specified with tR= tF= 20 ns (10% to 90% of +5.0 V) and timed from a voltage level of 1.6 V. 9/ t4, t10, t11, and t12are measured with the load circuits of figures 8 and 9 and defined as the time required for an output to cross 0.8 V or 2.4 V. 10/ t13is defined as the time required fo

44、r the data lines to change 0.5 V when loaded with the circuits of figure 10. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89698 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 8 DSCC

45、 FORM 2234 APR 97 Device type 01 02 Case outline L Terminal number Terminal symbol 1 VIN(+)A VIN(+)A 2 VIN(+)B VIN(+)B 3 VIN(-)A VIN(-)A 4 VIN(-)B VIN(-)B 5 VREF VREF 6 AGND AGND 7 CS CS 8 WR WR 9 RD RD 10 INT see note INT see note 11 CLK CLK 12 DGND DGND 13 HBEN RDY see note 14 RDY see note DB0 (LS

46、B) 15 DB0 (LSB) DB1 16 DB1 DB2 17 DB2 DB3 18 DB3 DB4 19 DB4 DB5 20 DB5 DB6 21 DB6 DB7 22 DB7 (MSB) DB8 23 I.C. DB9 (MSB) 24 VDD VDD NOTES: 1. INT and RDY are open-drain outputs and need 3.0 k external pull-up resistors for operation. 2. I.C. = internally connected. FIGURE 1. Terminal connections. Pr

47、ovided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89698 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 9 DSCC FORM 2234 APR 97 Device type 01 CS WR RD HBEN Function 1 X X X Not selected 0

48、1 1 X Selected, wait for WR , RD 0 1 X Start conversion on falling edge of WR 0 1 0 0 Enable ADC data (8 LSBs), data is right justified 0 1 0 1 Enable ADC data (2 LSBs), data is right justified Device type 02 CS WR RD Function 1 X X Not selected 0 1 1 Selected, wait for WR , RD 0 1 Start conversion on falling edge of WR 0 1 0 Enable ADC data (10 bits) 1 = high logic level 0 = low logic level X = irrelevant = one clock cycle