DLA SMD-5962-89616 REV D-2013 MICROCIRCUIT LINEAR CMOS 8-BIT A D CONVERTER MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Added vendor CAGE 1ES66 to devices 03 and 04. Made changes to table I. Editorial changes throughout. 90-12-03 Michael Frye B Drawing updated to reflect current requirements. - lgt 01-07-16 Raymond Monnin C Clock input low current in Table I was c

2、orrected to reflect the correct unit. - lgt 01-09-21 Raymond Monnin D Redrawn. Paragraphs updated to current MIL-PRF-38535 requirements. - drw 13-01-25 Charles F. Saffle THE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED. REV SHEET REV D D SHEET 15 16 REV STATUS REV D D D D D D D D D D D D D

3、 D OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Rick Officer DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE CHECKED

4、 BY Raymond Monnin APPROVED BY Michael A. Frye MICROCIRCUIT, LINEAR, CMOS 8-BIT A/D CONVERTER, MONOLITHIC SILICON DRAWING APPROVAL DATE 89-07-12 AMSC N/A REVISION LEVEL D SIZE A CAGE CODE 67268 5962-89616 SHEET 1 OF 16 DSCC FORM 2233 APR 97 5962-E218-13 Provided by IHSNot for ResaleNo reproduction o

5、r networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89616 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class l

6、evel B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-89616 01 V A Drawing number Device type (see 1.2.1) Case outline (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device types. The device typ

7、es identify the circuit function as follows: Device type Generic number Circuit function 01 AD-908A CMOS microprocessor-compatible FAST 8-bit A/D converter 02 AD-908B CMOS microprocessor-compatible FAST 8-bit A/D converter 03 PM-7574A CMOS microprocessor-compatible 8-bit A/D converter 04 PM-7574B CM

8、OS microprocessor-compatible 8-bit A/D converter 1.2.2 Case outlines. The case outlines are as designated in MIL-STD-1835 as follows: Outline letter Descriptive designator Terminals Package style V GDIP1-T18 or CDIP2-T18 18 Dual-in-line 2 CQCC1-N20 20 Square leadless chip carrier 1.2.3 Lead finish.

9、The lead finish is as specified in MIL-PRF-38535, appendix A. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89616 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 3 DSCC FORM 2234 APR

10、97 1.3 Absolute maximum ratings. VDDto AGND . 0 V dc to +7.0 V dc VDDto DGND . 0 V dc to +7.0 V dc AGND to DGND 0.3 V dc Digital input voltage (RD , CS pins) to DGND. -0.3 V dc to VDDDigital output voltage (DB0 DB7, BUSY pins) to DGND -0.3 V dc to VDDClock input voltage to (CLK pins) DGND -0.3 V dc

11、to VDDVoltage at VREF-0 V dc to -20 V dc Voltage at VBOFS20 V dc Voltage at VAIN20 V dc Power dissipation (PD): To +75C . 450 mW Derate above +75C (cases V and 2) 6.0 mW/C Storage temperature range . -65C to +150C Lead temperature (soldering, 10 seconds) +300C Thermal resistance, junction to case (J

12、C). See MIL-STD-1835 Thermal resistance, junction to ambient (JA) Cases V and 2 . 35C/W 1.4 Recommended operating conditions. Supply voltage (VDD) . +5 V dc Reference voltage (VREF) -10 V dc Ground AGND = DGND = 0 V dc Clock resistance (RCLK): Devices 01 and 02 . 43 k Devices 03 and 04 . 150 k Clock

13、 capacitance (CCLK) 100 pF Ambient operating temperature range (TA) . -55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise speci

14、fied, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Int

15、erface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.dla.mil/quicksearch/ or from the Standardization

16、Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicabl

17、e laws and regulations unless a specific exemption has been obtained. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89616 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 4 DSCC FORM 2

18、234 APR 97 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and q

19、ualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Qu

20、ality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to

21、 identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 Termi

22、nal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth tables. The truth tables shall be as specified on figure 2. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I a

23、nd shall apply over the full ambient operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF

24、-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the d

25、evice. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the

26、QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DLA Land and Maritime -VA prior to listing as a

27、n approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircu

28、its delivered to this drawing. 3.8 Notification of change. Notification of change to DLA Land and Maritime -VA shall be required for any change that affects this drawing. 3.9 Verification and review. DLA Land and Maritime, DLA Land and Maritimes agent, and the acquiring activity retain the option to

29、 review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-

30、89616 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions -55C TA+125C VDD= +5 V, VREF= -10 V, AGND = DGND = 0 V Unipolar configuration Group A subgroups Device type Limits Unit unless

31、otherwise specified Min Max Integral nonlinearity INL 1, 2, 3 01, 03 0.5 LSB 1/ 02, 04 0.75 Differential nonlinearity DNL 1, 2, 3 01, 03 0.75 LSB 1/ 02, 04 0.875 Gain error 2/ AE 1 01, 03 3.0 LSB 02, 04 5.0 2, 3 01, 03 4.5 02, 04 6.5 Offset error VOS 1 01, 03 30.0 mV 02, 04 60.0 2, 3 01, 03 50.0 02,

32、 04 80.0 Resistance mismatch BOFSto AAINRAB1, 2, 3 01, 02 1.0 % 03, 04 1.5 Input resistance RINVREFpins 1, 2, 3 All 5 15 k BOFS pins 10 30 AIN pins 10 30 Digital input high level VIHRD , CS 3/ 1, 2, 3 All 2.4 V Digital input low level VILRD , CS 3/ 1, 2, 3 All 0.8 V Digital input current IINVIN= 0 V

33、 or VDD1 All 1.0 A 2, 3 10.0 Clock input high level VIHClock 3/ 1, 2, 3 01, 02 2.4 V 03, 04 3.0 Clock input low level VILClock 3/ 1, 2, 3 01, 02 0.8 V 03, 04 0.4 Clock input high current IIHClock, VIN= VDD1 All 2.0 mA Clock input low current IILClock, VIN= 0 V 1 All 1.0 A 2, 3 10.0 See footnotes at

34、end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89616 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristi

35、cs - continued. Test Symbol Conditions -55C TA+125C VDD= +5 V, VREF= -10 V, AGND = DGND = 0 V Unipolar configuration Group A subgroups Device type Limits Unit unless otherwise specified Min Max Digital output high level DB7 DB0; BUSY VOHISOURCE= 40 A 1, 2, 3 All 4.0 V Digital output low level DB7 DB

36、0; BUSY VOLISINK= 1.6 mA 1, 2, 3 All 0.4 V Floating state leakage current (DB7 DB0) ILKGV0= 0 V or VDD1 All 1.0 A 2, 3 10.0 Supply current from VDDIDDAIN= 0 V, BUSY and RD 1, 2, 3 01, 02 2.5 mA high 03, 04 5.0 Digital input capacitance CINSee 4.3.1c 4 All 5.0 pF Floating state output capacitance (DB

37、7 DB0) COUTSee 4.3.1c 4 All 7.0 pF Functional test See 4.3.1d 7, 8 All CS pulse width 4/ tCS9 01, 02 60 ns 10, 11 90 9, 10, 11 03, 04 150 RD to CS setup time 5/ tWSCS9, 10, 11 All 0 ns CS to BUSY tCBPDBUSY load = 20 pF 9 01, 02 120 ns propagation delay 5/ 03, 04 180 ns 10, 11 01, 02 150 03, 04 180 B

38、USY load = 100 pF 9 01, 02 150 03, 04 200 10, 11 All 200 BUSY to RD setup time 4/ tBSR9, 10, 11 All 0 ns BUSY to CS setup time 4/ tBSCS9, 10, 11 All 0 ns Data valid propagation tRADLoad = 20 pF 9 01, 02 140 ns delay 4/ 10, 11 200 9, 10, 11 03, 04 220 See footnotes at end of table. Provided by IHSNot

39、 for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89616 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - continued. Test Symbol Cond

40、itions -55C TA+125C VDD= +5 V, VREF= -10 V, AGND = DGND = 0 V Unipolar configuration Group A subgroups Device type Limits Unit unless otherwise specified Min Max Data valid tRADLoad = 100 pF 9 01, 02 170 ns propagation delay 5/ 10, 11 230 9, 10, 11 03, 04 400 Data valid hold time tRHD9 01, 02 30 100

41、 ns 4/ 10, 11 40 140 9, 10, 11 03, 04 80 180 CS to RD hold time tRHCS9 01, 02 200 ns 4/ 10, 11 250 9, 10, 11 03, 04 500 Reset time tRESET9 01, 02 450 ns requirement 4/ 10, 11 500 9, 10, 11 03, 04 3.0 s RD to BUSY tWBPDBUSY load = 20 pF 9 01, 02 600 ns propagation delay 4/ 10, 11 800 9, 10, 11 03, 04

42、 2 s Conversion time tC9, 10, 11 01, 02 6 s 1/, 5/ 03, 04 15 1/ Devices 01 and 02 measured using external clock frequency of 1.35 MHz. Devices 03 and 04 measured using external clock frequency of 550 kHz. See timing waveforms on figure 3. 2/ Gain error is measured after calibration out offset error.

43、 3/ Guaranteed by functional pattern testing in external clock RAM, ROM, and SLOW modes. 4/ Static RAM interface mode. 5/ If not tested, shall be guaranteed to the limits specified in table I. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD

44、MICROCIRCUIT DRAWING SIZE A 5962-89616 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 8 DSCC FORM 2234 APR 97 Device type 01, 02, 03, and 04 Case outline V 2 Terminal number Terminal symbol 1 VDD NC 2 VREF VDD 3 BOFS VREF 4 AIN BOFS 5 AGND AIN 6 DB7 AGND 7 DB6 DB7 8 DB5 DB6 9

45、 DB4 DB5 10 DB3 DB4 11 DB2 NC 12 DB1 DB3 13 DB0 DB2 14 BUSY DB1 15 RD DB016 CS BUSY 17 CLK RD 18 DGND CS 19 - CLK 20 - DGND NC = No connection FIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWI

46、NG SIZE A 5962-89616 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 9 DSCC FORM 2234 APR 97 Device types 01 and 02. Static RAM mode Inputs Outputs Operation CS RD BUSY DB7 DB0L H H High Z Start convert (write cycle) L H High Z to Data Read data (read cycle) L H Data to High Z

47、 Reset converter H X (See note) X High Z No effect (not selected) L H L High Z No effect (converter busy) L L High Z No effect (converter busy) L L High Z Conversion error not allowed (See note) L = Low H = High X = Dont care = Low to high transition = High to low transition NOTE: If RD goes LOW to

48、HIGH, the ADC is internally reset, regardless of the states of CS or BUSY . FIGURE 2. Truth tables. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89616 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 10 DSCC FORM 2234 APR 97 Device types 03 and 04. Static RAM mode Inputs Outputs Operation CS RD BU