DLA SMD-5962-88766 REV A-2004 MICROCIRCUIT DIGITAL-LINEAR 12-BIT CMOS DIGITAL TO ANALOG CONVERTER WITH OUTPUT AMPLIFIER AND REFERENCE MONOLITHIC SILICON《硅单片输出扬声器参考12位互补型金属氧化物半导体数字类.pdf

《DLA SMD-5962-88766 REV A-2004 MICROCIRCUIT DIGITAL-LINEAR 12-BIT CMOS DIGITAL TO ANALOG CONVERTER WITH OUTPUT AMPLIFIER AND REFERENCE MONOLITHIC SILICON《硅单片输出扬声器参考12位互补型金属氧化物半导体数字类.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-88766 REV A-2004 MICROCIRCUIT DIGITAL-LINEAR 12-BIT CMOS DIGITAL TO ANALOG CONVERTER WITH OUTPUT AMPLIFIER AND REFERENCE MONOLITHIC SILICON《硅单片输出扬声器参考12位互补型金属氧化物半导体数字类.pdf（11页珍藏版）》请在麦多课文档分享上搜索。

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Update drawing to current requirements. Editorial changes throughout. - drw 04-07-14 Raymond Monnin REV SHET REV SHET REV STATUS REV A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 PMIC N/A PREPARED BY Dan Wonnell DEFENSE SUPPLY CENTER C

2、OLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Raymond Monnin COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Raymond Monnin MICROCIRCUIT, DIGITAL-LINEAR, 12-BIT CMOS DIGITAL TO ANALOG CONVERTER WITH, AND AGENCIES OF THE DEPARTMENT

3、OF DEFENSE DRAWING APPROVAL DATE 98-10-14 OUTPUT AMPLIFIER AND REFERENCE, MONOLITHIC SILICON AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 67268 5962-88766 SHEET 1 OF 10 DSCC FORM 2233 APR 97 5962-E336-04 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-ST

4、ANDARD MICROCIRCUIT DRAWING SIZE A 5962-88766 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-P

5、RF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-88766 01 L A Drawing number Device type (see 1.2.1) Case outline (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device types. The device types identify the circuit function as follows:

6、Device type Generic number Circuit function 01 AD7245A 12-Bit CMOS DAC with output amplifier and reference; parallel loading structure 02 AD7248A 12-Bit CMOS DAC with output amplifier and reference; 8+4 loading structure 1.2.2 Case outlines. The case outlines are as designated in MIL-STD-1835 and as

7、 follows: Outline letter Descriptive designator Terminals Package style 3 CQCC1-N28 28 Square leadless chip carrier L GDIP3-T24 or CDIP4-T24 24 Dual-in-line R GDIP1-T20 or CDIP2-T20 20 Dual-in-line 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum

8、ratings. 1/ Positive supply voltage (VDD) to AGND -0.3 V dc to +17.0 V dc Positive supply voltage (VDD) to DGND . -0.3 V dc to +17.0 V dc VDDto VSS. -0.3 V dc to +34.0 V dc AGND to DGND. -0.3 V dc to VDDDigital input voltage to DGND -0.3 V dc to VDD+ 0.3 V dc VOUTto AGND VSSto VDDVOUTto VSS. 0 V dc

9、to +24.0 V dc VOUTto VDD. -32 V to 0 V dc Voltage reference output (REF OUT) to AGND 0 v to VDDPower dissipation to +75C 2/ . 450 mW Storage temperature -65C to +150C Lead temperature (soldering, 10 sec) +300C 1/ Stresses above absolute maximum rating may cause permanent damage to the device. Extend

10、ed operation at the maximum levels may degrade performance and affect reliability. 2/ Above +75C, derate at a factor of 6 mW/C. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88766 DEFENSE SUPPLY CENTER COLUMB

11、US COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions. Single supply: Positive supply voltage (VDD) +15 V 5% Negative supply voltage (VSS). 0 V AGND = DGND 0 V Dual supply: Positive supply voltage (VDD) +12 V to +15 V 5% Negative supply volt

12、age (VSS). -12 V to -15 V 5% AGND = DGND 0 V Load resistance (RL) 2 k to GND Load capacitance (CL) . 100 pF to GND REF OUT . unloaded Ambient operating temperature range. -55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standa

13、rds, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.

14、 DEPARTMENT OF DEFENSE STANDARADS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of t

15、hese documents are available online at http:/assist.daps.dla.mil/quicksearch/ or www.dodssp.daps.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing an

16、d the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-STAND

17、ARD MICROCIRCUIT DRAWING SIZE A 5962-88766 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B d

18、evices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manu

19、facturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modif

20、ications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specifi

21、ed in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth tables. The truth tables shall be as specified on figure 2. 3.3 Electrical

22、performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full ambient operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specifie

23、d in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of

24、 the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The

25、compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved sourc

26、e of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformanc

27、e. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DSCC-VA shall be required for any change that affects this drawing. 3.9 Verification and review.

28、DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted witho

29、ut license from IHS-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88766 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ -55C TA +125C unless otherwise specified Group A su

30、bgroups Device type Limits Unit Min MaxResolution RES 1, 2, 3 All 12 Bits Relative accuracy RA VDD= +11.4 V to +15.75 V VSS= -11.4 V to -15.75 V 1, 2, 3 All -1 +1 LSB Differential nonlinearity DNL Guaranteed monotonic 1, 2, 3 All -1 +1 LSB Unipolar offset error UOE VSS= 0 V or -11.4 V to -15.75 V 1,

31、 2, 3 All -5 +5 LSB DAC gain error 2/ GE 1, 2, 3 All -2 +2 LSB Full scale output voltage VOUTE VDD= +15 V 1 All -.2 +.2 %FSR error 3/ 2, 3 -.6 +.6 Full scale/VDDVDD= +10.8 V to +16.5 V 1 All -.06 +.06 %FSR/V Full scale/VSSVSS= -10.8 V to -16.5 V 1 All -.01 -.01 %FSR/V Reference output VREFOUTVDD= +1

32、5 V, VSS= -15 V 1 All 4.99 5.01 V Reference/VDDVDD= +10.8 V to +16.5 V 1 All 2 mV/V Reference load sensitivity Reference load current change (0-100 A). Not including ROFScurrent. 1, 2, 3 All -1.0 +1.0 mV Digital input high voltage VINH1, 2, 3 All 2.4 V Digital input low voltage VINL1, 2, 3 All 0.8 V

33、 Digital input current for data and control inputs 4/ IINVIN= 0 or VDD1, 2, 3 All -10 +10 A Digital input capacitance CINsee 4.3.1b 4 5/ All 8 pF Output range resistors ROUT1, 2, 3 All 15 30 Output ranges 6/ Pin strappable 1, 2, 3 All 0 5 V Minimum load resistance 0 10 2 k to GND -5 +5 Power supply

34、current IDDOutput unloaded 1, 2, 3 All 12 mA ISS5 Functional tests see 4.3.1c 7, 8 All Output voltage settling positive and negative full scale change 7/ tSLTo 0.5 LSB, RL= 2 k, see 4.3.1b 4 5/ All 10 s Output voltage slew rate SR see 4.3.1b 4, 5, 6 5/ All 1.5 V/s See footnotes at end of table. Prov

35、ided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88766 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - contin

36、ued. Test Symbol Conditions 1/ -55C TA +125C unless otherwise specified Group A subgroups Device type Limits Unit Min MaxChip select pulse width t19, 10, 11 All 100 ns Write pulse width t29, 10, 11 All 100 ns Chip select to write setup t39, 10, 11 All 0 ns Chip select to write hold t49, 10, 11 All 0

37、 ns Data valid to write setup time t59, 10, 11 All 80 ns Data valid to write hold time t69, 10, 11 All 10 ns Load DAC pulse width t79, 10, 11 All 100 ns Clear pulse width t89, 10, 11 01 100 ns 1/ Dual supply: VDD= 11.4 V to 15.75 V, VSS= 0 V or -11.4 V to -15.75 V, AGND = DGND = 0 V, RL= 2 k to GND,

38、 CL= 100 pF to GND. REF unloaded, unless otherwise stated. 2/ This error is calculated with respect to the reference voltage and is measured after the offset error has been allowed for. 3/ This error is calculated with respect to an ideal 4.9988 V (on the 5 V range) or 9.9976 V (on the 10 V range).

39、Typical full scale temperature coefficient is 30 ppm of FSSR/C. 4/ Control inputs are CS , WR , LDAC and CLR for device 01 and CSMSB , CSLSB , WR and LDAC for device 02. 5/ Subgroups 4, 5 and 6 shall be measured only for initial test, or after process or design changes which may affect the parameter

40、 in those subgroups. 6/ 0 to +10 applies to VDD= +15 V 5% only, and VSS= -15 V 5%. 7/ For positive full scale change, DAC register loaded all 0s to all 1s. For negative full scale change, DAC register loaded all 1s to all 0s. Provided by IHSNot for ResaleNo reproduction or networking permitted witho

41、ut license from IHS-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88766 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 7 DSCC FORM 2234 APR 97 Device type 01 02 Case outlines 3 L R Terminal number Terminal symbol 1 NC VSSVSS2 VSSROFSROFS3 ROFSREF OUT REF OUT 4 REF OUT

42、AGND AGND 5 AGND DB11 (MSB) DB7 6 DB11 DB10 DB6 7 DB10 DB9 DB5 8 NC DB8 DB4 9 DB9 DB7 DB3 10 DB8 DB6 DGND 11 DB7 DB5 DB2 12 DB6 DGND DB1 13 DB5 DB4 (LSB) DB0 14 DGND DB3 CSMSB 15 NC DB2CSLSB 16 DB4 DB1 WR 17 DB3 DB0 LDAC 18 DB2 CS VDD19 DB1 WR RFB20 DB0 LDAC VOUT21 CS CLR 22 NC VDD23 WR RFB24 LDAC V

43、OUT25 CLR 26 VDD27 RFB28 VOUTFIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88766 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 8 DSCC FORM 223

44、4 APR 97 Device type 01 CLR LDAC WR CS Function H L L L Both latches are transparent H H H X Both latches are latched H H X H Both latches are latched H H L L Input latches are transparent H H _ L Input latches are latched H L H H DAC latches are transparent H _ H H DAC latches are latched L X X X D

45、AC latches loaded with all 0s _ H H H DAC latches loaded with all 0s and output remains at 0 V 0r -5 V _ L L L Both latches are transparent and output follows input data H = High state L = Low state X = Dont care Device type 02 CSLSB CSMSB WR LDAC Function L H L H Loads LS byte into input latch L H

46、_ H Latches LS byte into input latch _ H L H Latches LS byte into input latch H L L H Loads MS nibble into input latch H L _ H Latches MS nibble into input latch H _ L H Latches MS nibble into input latch H H H L Loads input latch into DAC latch H H H _ Latches input latch into DAC latch H L L L Loa

47、ds MS nibble into input latch and Loads input latch into DAC latch H H H H No data transfer operation H = High state L = Low state X = Dont care FIGURE 2. Truth tables. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-STANDARD MICROCIRCUIT DRAWING SIZE

48、A 5962-88766 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 9 DSCC FORM 2234 APR 97 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition A, B,