DLA SMD-5962-88740 REV D-2007 MICROCIRCUIT MEMORY DIGITAL CMOS 2K X 8 STATIC RAM MONOLITHIC SILICON《硅单片2K X 8静态RAM 互补型金属氧化物半导体数字存储微电路》.pdf

《DLA SMD-5962-88740 REV D-2007 MICROCIRCUIT MEMORY DIGITAL CMOS 2K X 8 STATIC RAM MONOLITHIC SILICON《硅单片2K X 8静态RAM 互补型金属氧化物半导体数字存储微电路》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-88740 REV D-2007 MICROCIRCUIT MEMORY DIGITAL CMOS 2K X 8 STATIC RAM MONOLITHIC SILICON《硅单片2K X 8静态RAM 互补型金属氧化物半导体数字存储微电路》.pdf（15页珍藏版）》请在麦多课文档分享上搜索。

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add vendor CAGE number 75569 to the drawing. Add vendor CAGE number 6Y440 to device types 03LX, 03XX, 04LX, and 04XX. Removed Vendor CAGE number OBK02 from drawing as approved source of supply. Editorial changes throughout. 89-10-16 Michael A. Fr

2、ye B Changes in accordance with NOR 5962-R160-92 92-03-23 Michael A. Frye C Update drawing to reflect current requirements. Add tPU, tPD, tWLQZ, and tWHQXto table I. Editorial changes throughout. - gap 01-01-12 Raymond Monnin D Boilerplate update and part of five year review. tcr 07-02-13 Joseph Rod

3、enbeck THE FRONT PAGE OF THIS DRAWING HAS BEEN REPLACED REV SHET REV SHET REV STATUS REV D D D D D D D D D D D D D D OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Kenneth S. Rice DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Wm J. Johnson COLUMBUS, O

4、HIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael A. Frye MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 2K X 8 STATIC RAM, MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 89-02-08 AMSC N/A REVISION LEVEL D SIZE A

5、CAGE CODE 67268 5962-88740 SHEET 1 OF 14 DSCC FORM 2233 APR 97 5962-E259-07.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88740 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEE

6、T 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-8874

7、0 01 L X Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function Access time 01 6116L, P4C116L 2K X 8 low power CMOS SRAM 35 ns 02 6116L, P4C116

8、L 2K X 8 low power CMOS SRAM 25 ns 1.2.2 Case outlines. The case outlines are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style J GDIP1-T24 or CDIP2-T24 24 Dual-in-line package K GDFP2-F24 or CDFP3-F24 24 Flat package L GDIP3-T24 or CDIP4-T24

9、 24 Dual-in-line package X CQCC1-N32 32 Rectangular leadless chip carrier Y See figure 1 24 Rectangular leadless chip carrier 3 CQCC1-N28 28 Square leadless chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. 1/ Supply voltage r

10、ange (VCC) . -0.5 V dc to 7 V dc Input voltage range 2/ 0.5 V dc to VCC+0.5 V dc Output voltage range in high impedance state -0.5 V dc to +7.0 V dc Output current . 20 mA Storage temperature range -65C to +150C Maximum power dissipation (PD) 1.0 W Lead temperature (soldering, 10 seconds) +275C Junc

11、tion temperature (TJ). +175C Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 1.4 Recommended operating conditions. Supply voltage range (VCC) . 4.5 V dc minimum to 5.5 V dc maximum High level input voltage (VIH) . +2.2 V dc minimum to VCC+0.5 V dc maximum Low level input voltage (VIL) -

12、0.5 V dc minimum to +0.8 V dc maximum Case operating temperature range (TC) . -55C to +125C 1/ All voltages are with respect to GND. 2/ VIL(minimum) of -3.0 V dc for short pulse durations of 20 ns or less. Prolonged operation at VILlevels below -1 V dc will result in excessive currents that may dama

13、ge the device. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88740 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Governm

14、ent specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATIO

15、N MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Mic

16、rocircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.

17、3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS

18、3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a

19、manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan

20、may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow

21、 option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.2 Truth table. The truth ta

22、ble shall be as specified on figure 3. 3.2.3 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.4 Die overcoat. Polyimide and silicone coatings are allowable as an overcoat on the die for alpha particle protection only. Each coated microcircuit inspection lot (see inspect

23、ion lot as defined in MIL-PRF-38535) shall be subjected to and pass the internal moisture content test at 5000 ppm (see method 1018 of MIL-STD-883). The frequency of the internal water vapor testing shall not be decreased unless approved by the preparing activity for class M. The TRB will ascertain

24、the requirements as provided by MIL-PRF-38535 for classes Q and V. Samples may be pulled anytime after seal. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88740 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO

25、 43218-3990 REVISION LEVEL D SHEET 4 DSCC FORM 2234 APR 97 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test require

26、ments. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition,

27、the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all

28、 non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be

29、required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535

30、, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DSCC-VA shall be required

31、for any change that affects this drawing. 3.9 Verification and review. DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 4.

32、VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. The foll

33、owing additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition C or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circ

34、uit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. (2) TA= +125C, minimum. b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical para

35、meter tests prior to burn-in are optional at the discretion of the manufacturer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88740 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D

36、 SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/, 2/ -55C TC+125C 4.5 V VCC 5.5 V VSS= 0 V Group A subgroups Device types Limits Unit unless otherwise specified Min Max 01 105 Operating supply current ICC1tAVAV= tAVAV(minimum), VCC = 5.5 V, CE

37、 = VIL, All other inputs at VIL1, 2, 3 02 115 mA 01 30 Standby power supply current TTL ICC2CE VIH, all other inputs VILor VIH, VCC= 5.5 V, f = 0 MHz 1, 2, 3 02 40 mA Standby power supply current CMOS ICC3CE (VCC-0.2 V), f = 0 MHz, VCC= 5.5 V, all other inputs (VCC-0.2 V) 1, 2, 3 All 0.9 mA Data ret

38、ention current ICC4CE (VCC-0.2 V), f = 0 MHz, VCC= 2.0 V, all other inputs (VCC-0.2 V) 1, 2, 3 All 300 A Input leakage current, any input IILKVCC= 5.5 V, VIN= 0 V to 5.5 V 1, 2, 3 All -10 10 A Off-state output leakage current IOLKVCC= 5.5 V, VIN= 0 V to 5.5 V 1, 2, 3 All -10 10 A Output high voltage

39、 VOHIOUT= -4.0 mA, VCC= 4.5 V, VIL= 0.8 V, VIH= 2.2 V 1, 2, 3 All 2.4 V Output low voltage VOLIOUT= 8.0 mA, VCC= 4.5 V, VIL= 0.8 V, VIH= 2.2 V 1, 2, 3 All 0.4 V Input capacitance 3/ CINVIN= 0 V, f = 1.0 MHz, TC= 25C, See 4.3.1c 4 All 8.0 pF Output capacitance 3/ COUTVOUT= 0 V, f = 1.0 MHz, TC= 25C,

40、See 4.3.1c 4 All 8.0 pF See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88740 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 6 DSCC FORM 2234 AP

41、R 97 TABLE I. Electrical performance characteristics Continued. Test Symbol Conditions 1/, 2/ -55C TC+125C 4.5 V VCC 5.5 V VSS= 0 V Group A subgroups Device types Limits Unit unless otherwise specified Min Max Read cycle time tAVAV4/ 5/ 9, 10, 11 01 35 ns 02 25 Address access time tAVQV9, 10, 11 01

42、35 ns 02 25 Output hold after tAVQX9, 10, 11 01 0 ns address change 3/ 02 0 Output enable to output tOLQX9, 10, 11 01 0 ns active 3/ 02 0 Output enable access tOLQV9, 10, 11 01 20 ns time 02 16 Chip enable to output tELQX9, 10, 11 01 0 ns active 3/ 02 0 Chip enable access time tELQV9, 10, 11 01 35 n

43、s 02 25 Chip enable to output tEHQZ9, 10, 11 01 20 ns in high - Z 3/ 02 15 Chip select to power-up tPU9, 10, 11 01 0 ns time 3/ 02 0 Chip deselect to power- tPD9, 10, 11 01 35 ns down time 3/ 02 25 Write recovery time tWHAV9, 10, 11 01 0 ns 02 0 Chip enable to end-of- tELWH9, 10, 11 01 30 ns write 0

44、2 20 Address valid to end-of- tAVWH9, 10, 11 01 30 ns write 02 20 Address to WE setup tAVWL9, 10, 11 01 0 ns time 02 0 Address to CE setup tAVEL9, 10, 11 01 0 ns time 02 0 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,

45、-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88740 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics Continued. Test Symbol Conditions 1/, 2/ -55C TC+125C 4.5 V VCC 5.5 V VSS= 0 V Group A subgroups De

46、vice types Limits Unit unless otherwise specified Min Max Output enable to output tOHQZ4/ 5/ 9, 10, 11 01 20 ns In high - Z 3/ 02 16 Write enable pulse width tWLWH9, 10, 11 01 25 ns 02 20 Data setup to tDVWH9, 10, 11 01 20 ns end-of-write 02 15 Data hold after tWHDX9, 10, 11 01 0 ns end-of-write 02

47、0 Chip enable pulse width tELEH9, 10, 11 01 30 ns during write 02 20 Write enable pulse setup tWLEH9, 10, 11 01 25 ns time 02 20 Write to output in high-Z tWLQZ9, 10, 11 01 20 ns 3/ 02 16 Output active from end tWHQX9, 10, 11 01 0 ns of write 3/ 02 0 1/ All voltages referenced to VSS. 2/ Negative un

48、dershoots to a minimum of -0.3 V are allowed with a maximum of 50 ns pulse width. 3/ Tested initially, and after any design or process change which could affect these parameters, and therefore shall be guaranteed to the limits specified in table I. 4/ AC measurements assume transition time 5 ns and input levels are from VSSto 3.0 V. Output load is specified on figure 4. Reference timing levels are at 1.5 V. 5/ For timing waveforms, see figure 4. Provided by I