DLA SMD-5962-88628 REV F-2013 MICROCIRCUIT DIGITAL CMOS BUS CONTROLLER REMOTE TERMINAL MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes in accordance with NOR 5962-R041-92. 91-11-25 M. L. Poelking B Changes in accordance with NOR 5962-R211-93. 93-08-13 M. L. Poelking C Add device class level V. Update boilerplate throughout. - LTG 97-07-17 T. M. Hess D Update boilerplate

2、to MIL-PRF-38535 requirements. - LTG 01-06-14 Thomas M. Hess E Update boilerplate to current MIL-PRF-38535 requirements. - CFS 07-06-11 Thomas M. Hess F Add device type 02. Add case outline U for flat pack. Add footnote 1/ for pin grid array package to figure 2. Update radiation features in section

3、1.5 and SEP table IB. Update boilerplate paragraphs to current MIL-PRF-38535 requirements. - MAA 13-03-11 Thomas M. Hess REV SHEET REV F F F F F F F F F F SHEET 15 16 17 18 19 20 21 22 23 24 REV STATUS REV F F F F F F F F F F F F F F OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED

4、 BY Todd D. Creek DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING CHECKED BY Ray Monnin THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Don Cool MICROCIRCUIT, DIGITAL, CMOS, BUS CONTROLLER REMOTE TERMINAL MONOLITHIC SIL

5、ICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 10 June 1988 AMSC N/A REVISION LEVEL F SIZE A CAGE CODE 67268 5962-88628 SHEET 1 OF 24 DSCC FORM 2233 APR 97 5962-E130-13Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MIC

6、ROCIRCUIT DRAWING SIZE A 5962-88628 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device class Q) and space application (device class V). A c

7、hoice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the following examples. For device class Q: 5962 - 88628 01

8、 X X Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2) Case outline (see 1.2.4) Lead finish (see 1.2.5) / / Drawing number For device class V: 5962 H 88628 01 V X X Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2) Device class designat

9、or Case outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(

10、s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 UT1553 BCRT Bus controller remote terminal 02 UT1553 BCRTB/BCRT Bus controller remote terminal Note: Device type 01 is a radiation hardened die, while device type 02 is not a radiation har

11、dened die. 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as listed below. Device class Device requirements documentation Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as d

12、esignated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style T CQCC1-F132 132 Unformed-lead chip carrier X CMGA15-P84 84 Pin grid array Y CQCC2-J84 84 “J” lead chip carrier Z CQCC1-N84 84 Square leadless chip carrier U See figure 1 84 Flat pack 1.2.5 Lead f

13、inish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88628 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET

14、 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ Supply voltage range -0.3 V dc to +7.0 V dc DC input/dc output voltage range . -0.3 V dc to (VCC) +0.3 V dc Storage temperature range -65C to +150C Maximum power dissipation (PD) 300 mW 2/ Maximum junction temperature (TJ) +175C Thermal resis

15、tance, junction-to-case (JC) See MIL-STD-1835 Latchup immunity (ILU) 150 mA Output short-circuit current (IOS): A(0-15), D(0-15), DMAR , DMACK , STDINTL , and HPINT . 100 mA All other outputs 200 mA 1.4 Recommended operating conditions. Supply voltage (VDD) . 4.5 V dc to 5.5 V dc Case operating temp

16、erature range (TC) -55C to +125C 1.5 Radiation features. For device type 01: Maximum total dose available (Dose rate = 50 300 rad(Si)/s): . 1 x 106Rads (Si) Single event phenomenon (SEP) : No SEU occurs at effective LET (see 4.4.4.5) . 55 MeV/(mg/cm2) 3/ No SEL occurs at effective LET (see 4.4.4.5)

17、. 80 MeV/(mg/cm2) 3/ Dose rate upset (20 ns pulse). 4/ Dose rate latchup . 4/ Dose rate survivability 4/ Neutron irradiated . 1 X 1014neutron/cm23/ 1.6 Digital logic testing for device classes Q and V. Fault coverage measurement of manufacturing logic tests (MIL-STD-883, test method 5012) . 86.5 per

18、cent _ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Must withstand the added PDdue to short circuit test, e.g. IOS. 3/ Limits are guaranteed by design or process but

19、 not production tested unless specified by the customer through the purchase order or contract. 4/ When characterized as a result of the procuring activities request, the condition will be specified. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-ST

20、ANDARD MICROCIRCUIT DRAWING SIZE A 5962-88628 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 4 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawi

21、ng to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883

22、 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:

23、/assist.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues

24、of the documents are the issues of the documents cited in the solicitation or contract. ASTM INTERNATIONAL(ASTM) ASTM F1192 - Standard Guide for the Measurement of Single Event Phenomena (SEP) Induced by Heavy Ion Irradiation of Semiconductor Devices (Copies of these documents are available online a

25、t http:/www.astm.org or from ASTM International 100 Barr Harbor Drive, P.O. Box C700, West Conshohocken, PA 19428-2959.) 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this do

26、cument, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device

27、 manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for dev

28、ice classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein and as specified on figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Functional b

29、lock diagram. The functional block diagram shall be as specified on figure 3. 3.2.4 Test circuit and switching waveforms. The test circuit and switching waveforms shall be as specified on figure 4. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STAN

30、DARD MICROCIRCUIT DRAWING SIZE A 5962-88628 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 5 DSCC FORM 2234 APR 97 3.2.5 Radiation exposure circuit. The radiation exposure circuit shall be maintained by the manufacturer under document revision level control and shall be made

31、available to the preparing and acquiring activity upon request. 3.2.6 Irradiation test connections. The irradiation test connections shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing and acquiring activity upon request. 3.3 Ele

32、ctrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table IA and shall apply over the full case operating temperature range. 3.4 Electrical tes

33、t requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table IA. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages

34、 where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with

35、MIL-PRF-38535. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in

36、 order to supply to the requirements of this drawing (see 6.6.1 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requiremen

37、ts of MIL-PRF-38535 and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 shall be provided with each lot of microcircuits delivered to this drawing. Provided by IHSNot for ResaleNo reproduction or networking permitted withou

38、t license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88628 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 6 DSCC FORM 2234 APR 97 TABLE IA. Electrical performance characteristics. Test Symbol Conditions 1/ 4.5 V VDD 5.5 V -55C TC +125C unless otherwise specified G

39、roup A subgroups Device type Limits Unit Min Max Low level input voltage, TTL inputs VIL1, 2, 3 All 0.8 V High level input voltage, TTL inputs 2/ VIH1, 2, 3 01 2.0 V 02 2.2 Input leakage current, TTL inputs IINVIN= VDDor VSS1, 2, 3 All -1 1 A M, D, P, L, R, F, G, H 1 01 -10 10 Inputs with pull down

40、resistors VIN= VDD1, 2, 3 All -1 1 M, D, P, L, R, F, G, H 1 01 -10 10 Inputs with pull-up resistors VIN= VSS1, 2, 3 01 -550 -80 02 -900 -150 M, D, P, L, R, F, G, H 1 01 -900 -150 Low level output voltage, TTL outputs VOLIOL= 3.2 mA 1, 2, 3 All 0.4 V High level output voltage, TTL outputs 9/ VOHIOH=

41、-400 A 1, 2, 3 All 2.4 V Three-state output leakage current TTL outputs IOZVOUT= VDDor VSS1, 2, 3 All -10 10 A Short-circuit output current 3/ 4/ IOSVDD= 5.5 V, VOUT= VDD1, 2, 3 All 100 mA VDD= 5.5 V, VOUT= 0 V 1, 2, 3 All -100 Quiescent current 5/ QIDD1, 2, 3 All 3 mA Input capacitance 6/ CINSee 4.

42、4.1c 4 All 15 pF Output capacitance 6/ COUT4 All 20 pF Bidirect I/O capacitance 6/ CIO4 All 25 pF Functional test See 4.4.1b 7, 8 All DMAG (L) to DMACK (L) tPHL1See figure 3. 7/ 9, 10, 11 All 0 45 ns MCLK (H) to RRD (L) tIOHL19, 10, 11 All 0 60 ns RWR (L) to DATA valid 8/ tOOZL19, 10, 11 01 0 30 ns

43、02 -5 30 MCLK (H) to MCLKD2 (H) tPLH19, 10, 11 All 0 40 ns MCLK (H) to RWR (L) tIOHL29, 10, 11 All 0 60 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88628 DLA LAND AND MAR

44、ITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 7 DSCC FORM 2234 APR 97 TABLE IA. Electrical performance characteristics - Continued. Test Symbol Conditions 1/ 4.5 V VDD 5.5 V -55C TC +125C unless otherwise specified Group A subgroups Device type Limits Unit Min Max RD + CS (L) to DATA valid

45、tPHL29, 10, 11 All 0 60 ns RD (L) to RRD (L) tPHL39, 10, 11 All 0 30 ns WR (L) to RWR (L) tPHL49, 10, 11 All 0 30 ns MEMSCI (L) to MEMSCO (L) tPHL59, 10, 11 All 0 30 ns 1/ RHA devices supplied to this drawing are characterized at all levels M, D, L, R, F, G and H of irradiation. However, this device

46、 is only tested at the H level. Pre and Post irradiation values are identical unless otherwise specified in Table IA. When performing post irradiation electrical measurements for any RHA level, TA= +25C. 2/ Radiation hardened technology shall have a VIHpre-irradiation of 2.2 V. 3/ Guaranteed to the

47、limit specified in table I, if not tested. 4/ Not more than one output may be shorted at a time for a maximum duration of one second. 5/ All inputs with internal pull-ups should be left floating. All other inputs should be tied high or low. 6/ The capacitance measurements shall be made between the i

48、ndicated terminal and ground at a frequency of 1 MHz at TCof +25C. The dc bias of the measuring instrument shall 0 0.1 V. The ac signal amplitude shall be less than 50 mV RMS. 7/ Switching tests are performed with VIH= VDDand VIL= 0.0 V as input test conditions and output transition times are measured at 1.4 V. 8/ Timing is not valid for RT timer field of message status word. The timer value may update during a DMA memory write. 9/ Signals DMAR, DMACK, HPINT, STDINTLare not tes