DLA SMD-5962-88610 REV F-2007 MICROCIRCUIT MEMORY DIGITAL CMOS 2K X 16 DUAL PORT SRAM MONOLITHIC SILICON《硅单片2K X 16双端口静态存取存储器互补型金属氧化物半导体数字存储微电路》.pdf

《DLA SMD-5962-88610 REV F-2007 MICROCIRCUIT MEMORY DIGITAL CMOS 2K X 16 DUAL PORT SRAM MONOLITHIC SILICON《硅单片2K X 16双端口静态存取存储器互补型金属氧化物半导体数字存储微电路》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-88610 REV F-2007 MICROCIRCUIT MEMORY DIGITAL CMOS 2K X 16 DUAL PORT SRAM MONOLITHIC SILICON《硅单片2K X 16双端口静态存取存储器互补型金属氧化物半导体数字存储微电路》.pdf（26页珍藏版）》请在麦多课文档分享上搜索。

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes to table I. Editorial changes throughout. 89-10-16 M.A. Frye B Add device types 05 and 06. Add case outline “U“ to drawing. Removed vendor CAGE 61772 as source of supply for case outline Y. Changes to table I. Editorial changes throughout

2、. 92-05-14 M.A. Frye C Add device types 07 through 12. Remove vendor CAGE 61772 as source of supply for device types 01 through 06 and add vendor CAGE 61772 as source of supply for device types 07 through 12. Add notes 6/ and 7/ to table I. Add notes to BUSY cycle waveforms. Editorial changes throug

3、hout. 93-09-16 M.A. Frye D Changes in accordance with NOR 5962-R132-94. 94-03-30 M. A. Frye E Changes to table I a.c. parameters based on updated die. Updated boilerplate. - glg 99-12-01 Raymond Monnin F Boilerplate update and part of five year review. tcr 07-07-11 Robert M. Heber THE FRONT PAGE OF

4、THIS DRAWING HAS BEEN REPLACED REV SHET REV F F F F F F F F F F SHEET 15 16 17 18 19 20 21 22 23 24 REV STATUS REV F F F F F F F F F F F F F F OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY James E. Jamison DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED B

5、Y Charles Reusing COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael A. Frye MICROCIRCUIT, MEMORY, DIGITAL, CMOS 2K X 16 DUAL PORT SRAM, MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 88-12-12

6、AMSC N/A REVISION LEVEL F SIZE A CAGE CODE 67268 5962-88610 SHEET 1 OF 24 DSCC FORM 2233 APR 97 5962-E401-07.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88610 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO

7、 43218-3990 REVISION LEVEL F SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in

8、 the following example: 5962-88610 01 X A Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function Access time 01 (see 6.6) 2K x 16 dual port CMO

9、S SRAM (master) 90 ns 02 (see 6.6) 2K x 16 dual port CMOS SRAM (slave) 90 ns 03 (see 6.6) 2K x 16 dual port CMOS SRAM (master) 70 ns 04 (see 6.6) 2K x 16 dual port CMOS SRAM (slave) 70 ns 05 (see 6.6) 2K x 16 dual port CMOS SRAM (master) 55 ns 06 (see 6.6) 2K x 16 dual port CMOS SRAM (slave) 55 ns 0

10、7 (see 6.6) 2K x 16 dual port CMOS SRAM (master) 90 ns 08 (see 6.6) 2K x 16 dual port CMOS SRAM (slave) 90 ns 09 (see 6.6) 2K x 16 dual port CMOS SRAM (master) 70 ns 10 (see 6.6) 2K x 16 dual port CMOS SRAM (slave) 70 ns 11 (see 6.6) 2K x 16 dual port CMOS SRAM (master) 55 ns 12 (see 6.6) 2K x 16 du

11、al port CMOS SRAM (slave) 55 ns 1.2.2 Case outlines. The case outlines are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style U See figure 1 68 flat pack X See figure 1 68 dual-in-line package Y CQCC1-N68 68 square leadless chip carrier Z CMGA

12、3-68 68 pin grid array 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Supply voltage range -0.5 V dc to +7.0 V dc Input voltage range -0.5 V dc to +6.0 V dc DC output current . 50 mA Storage temperature range . -65C to +150C Maximum pow

13、er dissipation (PD) 2.0 W Lead temperature (soldering, 10 seconds) +260C Thermal resistance, junction-to-case (JC) . Cases U and X . 37C/W Cases Y and Z See MIL-STD-1835 Junction temperature (TJ). +150C 1/ 1/ Maximum junction temperature may be increased to +175C during burn-in and steady-state life

14、. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88610 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 3 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions. Supply vol

15、tage range (VCC) . 4.5 V dc to 5.5 V dc High level input voltage range (VIH) . 2.2 V dc to 6.0 V dc Low level input voltage range (VIL) -0.5 V dc to +0.8 V dc 2/ Case operating temperature range (TC) . -55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The

16、following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufactur

17、ing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Micro

18、circuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict

19、 between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requir

20、ements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional ce

21、rtification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein

22、. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and ph

23、ysical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified

24、 on figure 2. 3.2.3 Truth tables. The truth tables shall be as specified on figure 3. 3.2.4 Block diagram. The block diagram shall be as specified on figure 4. 2/ VIL(min) = -3.0 V dc for pulse width less than 20 ns. Provided by IHSNot for ResaleNo reproduction or networking permitted without licens

25、e from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88610 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 4 DSCC FORM 2234 APR 97 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as spec

26、ified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordan

27、ce with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “

28、5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to ide

29、ntify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an a

30、pproved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits

31、 delivered to this drawing. 3.8 Notification of change. Notification of change to DSCC-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable requi

32、red documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method

33、5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition C or D. The test circuit shall be maintained by the manufacturer under document revision

34、level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. (2) TA= +125C, minimum. b. Interim a

35、nd final electrical test parameters shall be as specified in table II herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICR

36、OCIRCUIT DRAWING SIZE A 5962-88610 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions -55C TC+125C VCC= 4.5 V to 5.5 V Group A subgroups Device types Limits Unit unless otherw

37、ise specified Min Max Output high voltage VOHVCC = 4.5 V, IOH= -4.0 mA, VIL= 0.8 V, VIH= 2.2 V 1, 2, 3 All 2.4 V I/O0 I/O15IOL= 4.0 mA 1, 2, 3 All 0.4 V Output low voltage VOLVCC= 4.5 V, VIL= 0.8 V, VIH = 2.2 V, BUSY IOL= 16 mA 1, 2, 3 All 0.5 V Input leakage current ILIVCC= 5.5 V, GND VIN VCC1, 2,

38、3 All 10 A Output leakage current ILOVCC= 5.5 V, CE = VIH, GND VOUT VCC1, 2, 3 All 10 A 01-04 260 05,06 280 07-10 310 Dynamic operating current (both ports active) ICCVCC= 5.5 V, CE = VIL, f = fMAX1/, outputs open 1, 2, 3 11-12 315 mA 01-04 75 Standby power supply current (both ports- TTL input leve

39、ls) ISB1CELand CER VIH,VCC= 5.5 V, f = fMAX1/ 1, 2, 3 05,06 80 mA 01-04 170 05,06 180 07-10 200 Standby power supply current (one port- TTL input levels) ISB2VCC= 5.5 V, CELor CER VIH,f = fMAX1/, active port outputs open 1, 2, 3 11-12 210 mA Full standby power supply current (both ports-CMOS input l

40、evels) ISB3VCC= 5.5 V, f = 0 1/, CELand CER VCC -0.2 V, VIN VCC-0.2 V or 0.2 V 1, 2, 3 All 30 mA 01,02 155 03,04 160 05,06 170 07-10 190 Full standby power supply current (one port-CMOS input levels) ISB4VCC= 5.5 V, fMAX 1/, CELor CER VCC -0.2 V, VIN VCC,-0.2 V or 0.2 V active port outputs open 1, 2

41、, 3 11,12 200 mA Input capacitance CINVCC= 5.0 V, VIN =0 V, f = 1.0 MHz, TA= +25C, See 4.3.1c 4 All 11 pF See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88610 DEFENSE SUPPLY CE

42、NTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - continued. Test Symbol Conditions -55C TC+125C VCC= 4.5 V to 5.5 V Group A subgroups Device types Limits Unit unless otherwise specified Min Max Output capacitance

43、 COUTVCC = 5.0 V, VI/O = 0 V, f = 1.0 MHz, TA = +25C See 4.3.1c 4 All 11 pF Functional tests See 4.3.1d 7, 8A, 8B All 01,02, 07,08 90 03,04, 09,10 70 Read cycle time tRCSee figures 5 and 6. 2/ 9, 10, 11 05,06, 11,12 55 ns 01,02, 07,08 90 03,04, 09,10 70 Address access time tAASee figures 5 and 6. 2/

44、 9, 10, 11 05,06, 11,12 55 ns Output hold from address change tOHSee figures 5 and 6. 2/ 9, 10, 11 All 0 ns 01,02, 07,08 90 03,04, 09,10 70 Chip enable access time tACESee figures 5 and 6. 2/ 9, 10, 11 05,06, 11,12 55 ns 01-04, 07-10 40 Output enable access time tAOESee figures 5 and 6. 2/ 9, 10, 11

45、 05,06, 11,12 35 ns Output low Z time tLZSee figures 5 and 6. 3/ 4/ 9, 10, 11 All 5.0 ns 01-04, 07-10 25 Output high Z time tHZSee figures 5 and 6. 3/ 4/ 9, 10, 11 05,06, 11,12 20 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license f

46、rom IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88610 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - continued. Test Symbol Conditions -55C TC+125C VCC= 4.5 V to 5.5 V Group A subgroups D

47、evice types Limits Unit unless otherwise specified Min Max Chip enable to power-up time tPUSee figures 5 and 6. 2/ 3/ 9, 10, 11 All 0 ns Chip disable to power-down time tPDSee figures 5 and 6. 2/ 3/ 9, 10, 11 All 50 ns 01,02, 07,0890 03,04, 09,10 70 Write cycle time 5/ tWCSee figures 5 and 7. 2/ 9,

48、10, 11 05,06, 11,12 55 ns 01-04, 07-10 50 Chip enable to end of write tEWSee figures 5 and 7. 2/ 9, 10, 11 05,06, 11,12 40 ns 01-04, 07-10 50 ns Address valid to end of write tAWSee figures 5 and 7. 2/ 9, 10, 11 05,06, 11,12 40 ns Address setup time tASSee figures 5 and 7. 2/ 9, 10, 11 All 0 ns 01-02, 07-10 50 Write pulse widt