DLA SMD-5962-88595 REV B-2010 MICROCIRCUITS DIGITAL NMOS 256 X 4 STATIC RAM (SRAM) MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add the W package to the drawing. Changes on pages 1, 2, 6, 9, 10, 11, 12, and 13. Editorial changes throughout. 1989 APR 21 M. A. Frye B Updated boilerplate as part of 5-year review. - glg 10-08-30 Charles Saffle THE ORIGINAL FIRST SHEET OF THIS

2、 DRAWING HAS BEEN REPLACED. REV SHEET REV SHEET REV STATUS REV B B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/A PREPARED BY James E. Jamison DLA LAND AND MARITIME STANDARD MICROCIRCUIT DRAWING CHECKED BY Ray Monnin COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAW

3、ING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael A. Frye MICROCIRCUITS, DIGITAL, NMOS, 256 X 4 STATIC RAM (SRAM) MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 88-05-06 AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 67268 5962-88595 SHEET 1 OF 12 DSCC F

4、ORM 223 APR 97 5962-E347-10 .Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88595 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawi

5、ng describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-88595 | | Drawing Number 01 | | Device type (see 1.2.1) K |

6、| Case outline (see 1.2.2) X | | Lead finish (see (1.2.3) 1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type 01 Generic number (See 6.6) Circuit function 256 X 4 NMOS static RAM Access time 35 ns 1.2.2 Case outline(s). The case outline(s) are as designated

7、 in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style K GDFP2-F24 or CDFP3-F24 24 flat package W GDIP1-T22 or CDIP2-T22 22 dual-in-line package 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Supp

8、ly voltage range - - - - - - - - - - - - - - - - - DC voltage applied to outputs - - - - - - - - - - - DC input voltage range - - - - - - - - - - - - - - - - DC output current - - - - - - - - - - - - - - - - - - - - Storage temperature range - - - - - - - - - - - - - Maximum power dissipation (PD) 1

9、/ - - - - - - - Lead temperature (soldering, 10 seconds)- - - Thermal resistance, junction-to-case (JC): Cases K and W - - - - - - - - - - - - - - - - - - - Junction temperature (TJ)- - - - - - - - - - - - - - - -0.5 V dc to +7.0 V dc -0.5 V dc to +7.0 V dc -0.5 V dc to +7.0 V dc 20 mA -65C to +150C

10、 1.0 W 1/ +260C See MIL-STD-1835 +175C 1.4 Recommended operating conditions. Supply voltage range (VCC) - - - - - - - - - - - - - Case operating temperature range (TC) - - - - - 4.5 V dc to 5.5 V dc -55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The fol

11、lowing specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. 1/ Must withstand the added PDdue to short circuit test; e.g., IOS. Provided by IHSNot

12、 for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88595 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manu

13、facturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard

14、 Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of t

15、his drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in acc

16、ordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF

17、-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications

18、shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The

19、 design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.2 Truth table. The truth table shall be as specified on figure 2. 3.2.3 Case outlines. The case ou

20、tlines shall be in accordance with 1.2.2 herein. 3.3 Electrical performance characteristics. Unless otherwise specified, the electrical performance characteristics are as specified in table I and apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical t

21、est requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN m

22、ay also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built

23、in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufac

24、turer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DLA Land and Maritime -VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, app

25、endix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. Provided by IHSNot for ResaleNo reproduction or networking permitted without license

26、from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88595 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions -55C TC +125C VCC= 4.5 V to 5.5 V unless otherwise specified Group A sub

27、groups Device types Limits Unit Min Max Output high voltage VOH VCC= 4.5 V, IOH= -5.2 mA 1, 2, 3 All 2.4 V Output low voltage VOL VCC= 4.5 V, IOL= 8.0 mA 1, 2, 3 All 0.4 V Input high voltage VIH 1, 2, 3 All 2.1 VCC V Input low voltage VIL 1, 2, 3 All -2.5 0.8 V Input low current IIL VCC= 5.5 V, VIN=

28、 0 1, 2, 3 All -10 A Input high current IIH VCC= 5.5 V, VIN= 5.5 V 1, 2, 3 All 10 A Output current, high impedance IOZ VOL VOUT VOH, output disabled 1, 2, 3 All -50 50 A Output short circuit current 1/ IOS VCC= 5.5 V, VOUT= 0 V 1, 2, 3 All -25 -100 mA Power supply current (active) ICCVCC= 5.5 V, CS1

29、= WE = 0 V, CS2= OE = A0-A7= 5.0 V, IOUT= 0 mA 1, 2, 3 All 135 mA Input capacitance CIN VCC= 4.5 V, f = 1.0 MHz, TC= +25C, VIN= 0 V, See 4.3.1c 4 All 5.0 pF Output capacitance COUT 4 All 8.0 pF Chip select time tACS See figures 3 and 4 2/ 9, 10, 11 All 25 ns Chip select to high impedance tZRCS See f

30、igures 3 and 4 3/ 9, 10, 11 All 30 ns Output enable time tAOS See figures 3 and 4 2/ 9, 10, 11 All 25 ns Output enable to high impedance tZROS See figures 3 and 4 3/ 9, 10, 11 All 30 ns Address access time tAA See figures 3 and 4 2/ 9, 10, 11 All 35 ns Write disable to high impedance tZWS See figure

31、s 3 and 5 3/ 9, 10, 11 All 30 ns Write recovery time tWR See figures 3 and 5 2/ 9, 10, 11 All 25 ns See footnotes at end of table Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88595 DLA LAND AND MARITIME CO

32、LUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions -55C TC +125C VCC= 4.5 V to 5.5 V unless otherwise specified Group A subgroups Device types Limits Unit Min Max Write pulse width tW See figures

33、3 and 5 2/ 4/ 9, 10, 11 All 25 ns Data setup time prior to write tWSD See figures 3 and 5 2/ 9, 10, 11 All 5.0 ns Data hold time after write tWHD See figures 3 and 5 2/ 9, 10, 11 All 5.0 ns Address setup time tWSA See figures 3 and 5 2/ 4/ 9, 10, 11 All 5.0 ns Address hold time tWHA See figures 3 an

34、d 5 2/ 9, 10, 11 All 5.0 ns Chip select setup time tWSCS See figures 3 and 5 2/ 9, 10, 11 All 5.0 ns Chip select hold time tWHCS See figures 3 and 5 2/ 9, 10, 11 All 5.0 ns 1/ Not more than one output should be shorted at a time, and duration of short circuit shall not exceed 30 seconds. 2/ Test con

35、ditions assume signal transition times of 10 ns or less. Timing is referenced at input and output levels of 1.5 V. Output loading is equivalent to the specified IOL/IOHwith a load capacitance of 30 pF 3/ Test conditions assume signal transition times of 10 ns or less. Transition is measured at stead

36、y-state high level of -500 mV or steady-state low level of +500 mV on the output from 1.5 V level on the input with a load capacitance of 5.0 pF. 4/ tWis measured at tWSA= minimum. TWSAis measured at tW= minimum. Provided by IHSNot for ResaleNo reproduction or networking permitted without license fr

37、om IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88595 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 Device type 01 Case outlines K W Terminal number Terminal symbol 1 A3A32 A2A23 A1A14 A0A05 A5A56 A6A67 A7A78 VSS(GND) VSS(GND) 9 D1D110 010111 D2D

38、212 NC 0213 NC D314 020315 D3D416 030417 D4CS218 04OE 19 CS21CS 20 OE WE 21 1CS A422 WE VCC23 A4- 24 VCC- FIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88595 DLA LAND AND MAR

39、ITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 7 DSCC FORM 2234 APR 97 Device type 01 Input Output Mode OE 1CS CS2WE Dn0nX H X X X High Z Not selected X X L X X High Z Not selected L L H H X On Read stored data X L H L L High Z Write “0” X L H L H High Z Write “1” H L H H X High Z Output dis

40、abled H L H L L High Z Write “0” (output disabled) H L H L H High Z Write “1” (output disabled) H = Logic 1 state L = Logic 0 state X = Dont care HIGH Z = High impedance state FIGURE 2. Truth table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STA

41、NDARD MICROCIRCUIT DRAWING SIZE A 5962-88595 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 8 DSCC FORM 2234 APR 97 Measurement CL(including scope and jig capacitance) tZRCS. tZROS, and tZWS CL= 5.0 pF All others CL= 30 pF FIGURE 3. Output load circuit. Provided by IHSNot for

42、 ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88595 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 9 DSCC FORM 2234 APR 97 FIGURE 4. Read cycle timing diagram. Provided by IHSNot for ResaleNo reproduction

43、 or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88595 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 10 DSCC FORM 2234 APR 97 NOTE: Timing diagram represents one solution which results in an optimum cycle time. Timing may be cha

44、nged in various applications as long as the worst- case limits are not violated. FIGURE 5. Write cycle timing diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88595 DLA LAND AND MARITIME COLUMBUS, OHI

45、O 43218-3990 REVISION LEVEL B SHEET 11 DSCC FORM 2234 APR 97 3.8 Notification of change. Notification of change to DLA Land and Maritime -VA shall be required for any change that affects this drawing. 3.9 Verification and review. DLA Land and Maritime, DLA Land and Maritime s agent, and the acquirin

46、g activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with M

47、IL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883: (1) Test condition C o

48、r D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. (2) TA= +125C, minimum. b. Interim and final electrical test parameters shall be