DLA SMD-5962-88586 REV E-2012 MICROCIRCUIT HYBRID LINEAR MIL-STD-1553 BUS TO MICROPROCESSOR INTERFACE UNIT.pdf

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1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes to reflect MIL-H-38534 processing. Correction to table I. Editorial changes throughout. 92-03-05 Alan Barone B Changes in accordance with NOR 5962-R015-96. 95-12-08 Kendall A. Cottongim C Added device types 02 and 03 with cage code 88379.

2、 Made changes to table I, figure 1, and figure 20. Renumbered figures 5 through 21 to figures 4 through 20. Changes to reflect MIL-PRF-38534 processing. -sld 02-03-01 Raymond Monnin D Rewrite paragraphs 4.2.a.2. and 4.3.3.b.2 to add TC. 04-06-18 Raymond Monnin E Updated drawing paragraphs. -sld 12-0

3、1-13 Charles F. Saffle REV SHEET REV E E E E E E E E E E E E E E E E E E E SHEET 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 REV STATUS REV E E E E E E E E E E E E E E OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Robert M. Heber DLA LAND AND MARITIME COLUMBUS, O

4、HIO 43218-3990 http:/www.landandmaritime.dla.mil/ STANDARD MICROCIRCUIT DRAWING CHECKED BY Ray Monnin THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE APPROVED BY Michael Frye MICROCIRCUIT, HYBRID, LINEAR, MIL-STD-1553, BUS TO MICROPROCESSOR INTERFACE UN

5、IT DRAWING APPROVAL DATE 88-12-20 AMSC N/A REVISION LEVEL E SIZE A CAGE CODE 67268 5962-88586 SHEET 1 OF 33 DSCC FORM 2233 APR 97 5962-E056-12 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88586 DLA LAND AN

6、D MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents one product assurance class, class H (high reliability) and a choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PI

7、N). 1.2 PIN. The PIN shall be as shown in the following example: 5962-88586 01 X X Drawing number Device type Case outline Lead finish (see 1.2.1) (see 1.2.2) (see 1.2.3) 1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01

8、 BUS-66300II MIL-STD-1553, BUS to microprocessor interface unit 02 CT2566-001 MIL-STD-1553, BUS to microprocessor interface unit 03 CT2566-002 MIL-STD-1553, BUS to microprocessor interface unit 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline lette

9、r Descriptive designator Terminals Package style X See figure 1 78 Dual-in-line Y See figure 1 82 Flat pack 1.2.3 Lead finish. The lead finish shall be as specified in MIL-PRF-38534. 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) . -0.5 V dc to +7.0 V dc Input voltage range (VIN) -0.5 V

10、 dc to +7.0 V dc Supply current (ICC) . 150 mA Power dissipation (PD) . 250 mW 2/ Storage temperature range . -65 C to +150 C Lead temperature (soldering, 10 seconds) +300 C Thermal resistance, junction-to-case (qJC). 4.11 C/W 1.4 Recommended operating conditions. Supply voltage range (VCC) . 4.5 V

11、dc to 5.5 V dc Minimum logic high input voltage (VIH) 2.0 V dc Maximum logic low input voltage (VIL) . 0.8 V dc Case operating temperature range (TC) -55 C to +125 C Operating frequency (FOP) . 12.0 MHz 1/ Stresses above the absolute maximum ratings may cause permanent damage to the device. Extended

12、 operation at the maximum levels may degrade performance and affect reliability. 2/ Applies up to TC= +125 C.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88586 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-39

13、90 REVISION LEVEL E SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these document

14、s are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATIONS MIL-PRF-38534 - Hybrid Microcircuits, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard for Electronic Component Case O

15、utlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenu

16、e, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specif

17、ic exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item performance requirements for device class H shall be in accordance with MIL-PRF-38534. Compliance with MIL-PRF-38534 may include the performance of all tests herein or as designated in the device manufacturers

18、 Quality Management (QM) plan or as designated for the applicable device class. The manufacturer may eliminate, modify or optimize the tests and inspections herein, however the performance requirements as defined in MIL-PRF-38534 shall be met for the applicable device class. In addition, the modific

19、ation in the QM plan shall not affect the form, fit, or function of the device for the applicable device class. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38534 and herein. 3.2.1 Case outline(s). The case outl

20、ine(s) shall be in accordance with 1.2.2 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Block diagram. The block diagram shall be as specified on figure 3. 3.2.4 Timing diagram(s). The timing diagram(s) shall be as specified on figu

21、res 4 through 20. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full specified operating temperature range. Provided by IHSNot for ResaleNo reproduction or networking perm

22、itted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88586 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 4 DSCC FORM 2234 APR 97 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The elect

23、rical tests for each subgroup are defined in table I. 3.5 Marking of device(s). Marking of device(s) shall be in accordance with MIL-PRF-38534. The device shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers vendor similar PIN may also be marked. 3.6 Data. In addition to

24、 the general performance requirements of MIL-PRF-38534, the manufacturer of the device described herein shall maintain the electrical test data (variables format) from the initial quality conformance inspection group A lot sample, for each device type listed herein. Also, the data should include a s

25、ummary of all parameters manually tested, and for those which, if any, are guaranteed. This data shall be maintained under document revision level control by the manufacturer and be made available to the preparing activity (DLA Land and Maritime -VA) upon request. 3.7 Certificate of compliance. A ce

26、rtificate of compliance shall be required from a manufacturer in order to supply to this drawing. The certificate of compliance (original copy) submitted to DLA Land and Maritime -VA shall affirm that the manufacturers product meets the performance requirements of MIL-PRF-38534 and herein. 3.8 Certi

27、ficate of conformance. A certificate of conformance as required in MIL-PRF-38534 shall be provided with each lot of microcircuits delivered to this drawing. 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38534 or as modified in the

28、 device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88586 DLA L

29、AND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions -55 C TC+125 C unless otherwise specified Group A subgroups 1/ Device types Limits Unit Min Max Supply current ICCVCC= 5.5 V, IOH= -0.4 mA

30、, IOL= 4.0 mA, fIN= 12 MHz, measured at pin 20 1,2,3 All 150 mA High level output voltage 2/ VOHVCC= 4.5 V, IOH= -4.0 mA, VIH= 2.5 V, VIL= 0.4 V 1,2,3 All 3.7 V Low level output voltage 2/ VOLVCC= 4.5 V, IOL= 4.0 mA, VIH= 2.5 V, VIL= 0.4 V 1,2,3 All 0.4 V High level input current 3/ IIH1VCC= 5.5 V,

31、VIN= 2.5 V 1,2,3 All -10 +10 mA High level input current 4/ 5/ IIH2VCC= 5.5 V, VIH= 2.5 V 1,2,3 All -107 -630 mA Low level input current 3/ IIL1VCC= 5.5 V, VIN= 0.0V 1,2,3 All -10 +10 mA Low level input current 4/ 5/ IIL2VCC= 5.5 V, IIN= 0.0 V 1,2,3 All -134 -700 mA Functional tests 6/ VCC= 4.5 V, V

32、IH= 2.5 V, VIL= 0.4 V, IOH= -4.0 mA, IOL= 4.0 mA, f = 12 MHz 7,8 All Pass/Fail Delay timing: READY low delay (CPU handshake) tD1VCC= 4.5 V, VIH= 2.5 V, VIL= 0.4 V, IOH= -4.0 mA, IOL = 4.0 mA, fIN= 12 MHz, See figures 4 through 20 7/ 8/ 9,10,11 All 200 ns IOEN high delay (CPU handshake) tD29,10,11 Al

33、l 20 ns CPU MEMWR low delay tD39,10,11 All 120 ns CPU MEMOE low delay tD49,10,11 All 115 ns EXTLD low delay tD59,10,11 All 130 ns RESET low delay tD6 9,10,11 All 30 ns Internal Register delay (read) tD7 9,10,11 All 60 ns Internal Register delay (write) tD8 9,10,11 All 60 ns Register Data/Address set

34、up time tD99,10,11 All 40 ns Register Data/Address hold time tD109,10,11 All 0 ns BC , SOM cycle DMA mode tD119,10,11 All 120 ns INT low delay tD129,10,11 All 50 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDA

35、RD MICROCIRCUIT DRAWING SIZE A 5962-88586 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions -55 C TC+125 C unless otherwise specified Group A subgroups 1/ Device types Lim

36、its Unit Min Max Delay Timing - Continued: RTU, SOM cycle DMA delay tD13VCC= 4.5 V, VIH= 2.5 V, VIL= 0.4 V, IOH= -4.0 mA, IOL = 4.0 mA, fIN= 12 MHz, See figures 4 through 20 7/ 8/ 9,10,11 All 200 ns 1553 Command Word setup time tD149,10,11 All 60 ns 1553 Command Word hold time tD159,10,11 All 60 ns

37、MT , SOM cycle DMA delay tD169/ 9,10,11 All 200 ns CS low to MEMCS low delay tD179,10,11 All 30 ns OE low to MEMOE low delay tD189,10,11 All 30 ns WR low to MEMWR low delay tD199,10,11 All 30 ns BUSGRNT high delay tD209,10,11 All 25 ns BUSACK low address delay tD219,10,11 All 45 ns BUSACK high addre

38、ss delay tD229,10,11 All 25 ns Address increment delay tD239,10,11 All 200 ns Pulse Width Timing: READYD pulse width (CPU handshake) tPW1VCC= 4.5 V, VIH= 2.5 V, VIL= 0.4 V, IOH= -4.0 mA, IOL = 4.0 mA, fIN= 12 MHz, See figures 4 through 20 8/ 9,10,11 All 70 ns CPU MEMWR low pulse width tPW29,10,11 Al

39、l 70 ns CPU MEMCS low pulse width tPW39,10,11 All 70 ns EXTLD low pulse width tPW49,10,11 All 70 ns RESET low pulse width tPW59,10,11 All 70 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWI

40、NG SIZE A 5962-88586 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions -55 C TC+125 C unless otherwise specified Group A subgroups 1/ Device types Limits Unit Min Max Puls

41、e Width Timing - Continued: DMA MEMWR low pulse width tPW6VCC= 4.5 V, VIH= 2.5 V, VIL= 0.4 V, IOH= -4.0 mA, IOL = 4.0 mA, fIN= 12 MHz, See figures 4 through 20 8/ 9,10,11 All 70 ns DMA MEMCS low pulse width tPW79,10,11 All 70 ns BCSTART low pulse width tPW89,10,11 All 70 ns EOM low pulse width tPW99

42、,10,11 All 50 200 ns INT low pulse width tPW109,10,11 All 20 200 ns INT low ( BC EOM ) pulse width tPW119,10,11 All 60 ns SOM low pulse width tPW129,10,11 All 50 200 ns NBGRNT low pulse width tPW139,10,11 All 50 200 ns ADRINC low pulse width tPW149,10,11 All 50 200 ns MSTRCLR low pulse width tPW159,

43、10,11 All 150 ns DMA Cycle Data/Address set-up and hold timing: DMA address setup time tAS1VCC= 4.5 V, VIH= 2.5 V, VIL= 0.4 V, IOH= -4.0 mA, IOL = 4.0 mA, fIN= 12 MHz, See figures 4 through 20 7/ 8/ 9,10,11 All 40 ns DMA data setup time tDS1 9,10,11 All 83 ns DMA address setup time tAS29,10,11 All 4

44、5 ns DMA data setup time tDS29,10,11 All 83 ns DMA address hold time tAH19,10,11 All 60 ns DMA data hold time tDH19,10,11 All 30 ns DMA address hold time tAH29,10,11 All 0 ns DMA data hold time tDH29,10,11 All 0 ns Maximum clock frequency fMAX50 percent duty cycle 7/ 9,10,11 All 16.0 MHz See footnot

45、es on next page. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88586 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 8 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteri

46、stics -Continued. 1/ All group A subgroup testing may be performed concurrently. 2/ Measured at the following pins: Case X: Pins 3 through 5, 14, 16, 21 through 39, 42, 43, 45 through 47, 50, 56, 57, and 59 through 77. Case Y: Pins 5 through 8, 10, 11, 13, 15, 21, 28, 32, 33, 35, 39, and 45 through

47、81. 3/ Measured at the following pins: Case X: Pins 7 through 9, 11 through 13, 17, 19, 21 through 28, 38, 39, 44, 48, 49, 51, 53 through 55, 60 through 67 and 77. Case Y: Pins 9, 14, 16 through 19, 22 through 24, 26, 27,29, 31,34, 38, 45 through 47, and 66 through 81. 4/ Measured at the following p

48、ins: Case X: Pins 1, 2, 6, 10, 41, and 52. Case Y: Pins 2 through 4, 12, 20, and 25. 5/ For device type 03, case X, pin 52 and case Y, pin 25 have a 0.001 mf capacitor to ground. 6/ Functional tests performed to verify functionality of device as a handshake intermediary between MIL- STD-1750 Central Processing Units (CPU) and MIL-STD-1553 Bus Controller (BC), Remote Terminal Unit (RTU) and Bus Monitor (MT). 7/ Parameter shall be tested as part of device initial characterization and after design and process changes. Parameter shall be guaranteed to the limits specified in ta