DLA SMD-5962-87734 REV B-1992 MICROCIRCUIT DIGITAL CMOS CLOCK GENERATOR AND READY INTERFACE MONOLITHIC SILICON《硅单片准备接口时钟发生器互补型金属氧化物半导体数字微电路》.pdf

《DLA SMD-5962-87734 REV B-1992 MICROCIRCUIT DIGITAL CMOS CLOCK GENERATOR AND READY INTERFACE MONOLITHIC SILICON《硅单片准备接口时钟发生器互补型金属氧化物半导体数字微电路》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-87734 REV B-1992 MICROCIRCUIT DIGITAL CMOS CLOCK GENERATOR AND READY INTERFACE MONOLITHIC SILICON《硅单片准备接口时钟发生器互补型金属氧化物半导体数字微电路》.pdf（12页珍藏版）》请在麦多课文档分享上搜索。

1、32, -5 SMD-5962-87734 REV B 59 9999996 0032408 3 W A Changes to table 1. Editorial changes throughout. 90 JUN 28 B Changes to table I and switching waveforms. Editorial changes 92 NAY 14 I throughout. SHEET REV STATUS OF SHEETS PMLC NIA STANDARDIZED MILITARY DRAWING THIS DRAWING IS AVAILABLE FOR USE

2、 BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A PREPARED BY j)+y distribution is unlimited. 5962-E431 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-87734 REV B 59 m 999999b O012409 3 m - - 4 1. SCOPE 1.1 ;P:ups 1 13

3、IH q2/3 “IHR 1,2,3 ! VOL I IoL 5 sA 2/ hit V levi ce types All All At1 -I_ Al 1 All All All Test _. . t.1 a x ._-_- Nin 0.8 Input low voltage Input high voltage 2.8 2.6 V V - RES and FI input hfgh voltage 0.4: V RESET, PCLK output tow RESET, PCLK output high voltage voltage VOH 1 IOH = -1 LIA I 2.4

4、- HEADY, output low voltage CLK output low voltege CLK output high voltage Input leakage current _. _- - “II_. . ._I_ .I_- -. - OLR “OLC ILI IIL - OHC ALL ALL . . 4.Q -1 o All -30 nputsusining current on SO, SI pins j output CLIC frequency CTN Fc = 1 HHz, see 4.3.1 14 I I 7f8 See 4.3.ld, Vcc = 4.75

5、V, I 5.25 V All niR Power supply current Al 1 Input capacitance Functional tests All Oi 02 O3 - Ils ns ns ns -_- Il 5 ._ - _- - ns ns ns ns FI to CLK delay I I 9,10fq1 t, I At 1.5 V $/ I I - 22.5 28 40 22.5 28 35 . -_ -I . .- EFI tow time t2 I At 1.5 V A/ ?/ I I I I I I t3 I At 1.5 V $1 r/ 9,10,11 o

6、1 02 O3 o1 82 o3 - FI high time 50 ns o1 02 CLK period 62 500 ns 03 83 500 ns i 7f10f11 I 12 15 01 02 CLK low time ns ns ns - O3 20 STANDARDIZED MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 ESC FORM 193A JUL 91 I Provided by IHSNot for ResaleNo reproduction or networking per

7、mitted without license from IHS-,-,-: SMD-5762-87734 REV B 59 9999996 0012412 3 M I I 1 I l I O1 i 16 I I I At 3.6 V 21 4/ 6/ I/ CLK high time ns 02,03 I - I I I RES hold time I t16 I s/ 8/ i 9,10,11 i All i 10 i I ns READY inactive delay I tq7 1 At 0.8 V 2/ i 9,10,11 I All 1 01 I ns - I I I l I 25

8、I 1 ns I I - READY active delay I I I I I I I tI8 I At 0.8 V 2/ 1 9,10,11 j01,02 i O i 24 i ns 103 I O 133 Ins I I I - I I I 02 i 22 I I ns I I L I PCLK delay SIZE A 1 ,IO,II i 01 1 o i 35 i ns I I I I 102,03 I O I 45 1 ns 5962-87734 Reset delay 1 9,10,11 I O1 i 5 i 27 i ns - 102 I5 134 (ns 103 I5 I

9、50 Ins I I I I -_ See footnotes at end of table. STANDARDIZED MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 SHEET I 5 I REVISION LEVEL B ESC FORM 193A JUL 91 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-TABLE I. Electrical

10、performance characteristics - Continued. Group A /Device / Limits /Unit subgroups I .types 1-1 I Min I Max 1 I I I I 1- I 1 Test Conditions If i 1 -55C 5 TC.*12SoC I 4.75 V 5 Vci 5 5.25 V I I PCLK low time It21 I wu1 I 9.,10/11 I All lt4-20 I I ns I I I I I I I PCLK high time It22 1 B/U/ i I 9,10,11

11、 i All /t4-20 1 I ns I I I See figures 3 and.4. Due to test equipment limitations, actual tested values may differ from thace specified, but specified limits are guaranteed. Status lines and 3 excluded because they have internal pull-up resistors. CLK loading: When driving with EFI, provide minimum

12、EFI high and low times as fo CL = 100 pF. i CLK output frequency: 1 12 MHt i 16 MHz I I I i Min. required EFI high time i 35 ns 1 28 ns I Min. required EFI low time I 40 ns I 28 ns I l. * lows: I 20 MHr I 22.5 nsl 22.5 nsl I I -i _I With the internal crystal oscillator using recommended crystal and

13、capacitive loading, or with the EFI input meeting specifications t2 and t The recommended crystal loading for CLK frequencies of 3-16 IIHz are 25 pF from pin XI to ground, and 15 pF from pin X2 to ground. These recommended values are *5 pF and include all stray capacitance. device as possible. use a

14、 parallel-resonant, fundamental mode crystal. Decouple Vcc and GND as close to the When using crystal (with recommended capacitive loading per table below) appropriate for speed of the device, CLK output high and low times guaranteed to meet 5962-85148 requirements. Crystal frequency 1 to 8 MHz 8 to

15、 20 MHz I CI capacitance i 2 capacitance I (pin 7) 1 (pin 8) 1 60 PF I 40 PF I 25 PF I 15 PF 1 I Note: Capacitance values must include stray board capacitance. This is an asynchronous input. specif ic CLK edge. This specification is given for testing purposes only, to assure recognition at - READY l

16、oading: 5962-8514803 timing requirements and use 910n *5 percent pull-up resistor to meet 5962-8514801 and 5962-8514802 timing requi rements. IoL = 9 mA, CL = 150 pF. In system application, use 700n *5 percent pull-up resistor to meet PCLK and RESET loading: CL = 75 pF. PCLK also has 750n pull-up re

17、sistor. t4 refers to any allowable CLK period. SIZE 5962-87734 STANDARDIZED A MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL SHEET 6 B I I - I ESC FORM 193A JUL 91 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-

18、r s SMD-5962-87734 REV B 59 W 9999996 0012414 7 4. QUALITY ASSURANCE PROVISIONS 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with section 4 of MIL-M-38510 to the extent specified in MIL-STD-883 (see 3.1 herein). 4.2 Screening. Screening shall be in accordanc

19、e with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. shall apply: The following additional criteria a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition A, B, C, or D using the circuit submitted with the certificate of complianc

20、e (see 3.6 herein). (2) TA = +125OC, minimum. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. b. 4.3 Quality conformance inspection. Quality conforman

21、ce inspection shall be in accordance with method 5005 of MIL-STD-883 including groups A, B, C, and D inspections. criteria shall apply. The following additional 4.3.1 a. b. C. d. 4.3.2 a. b. Group A inspection. Tests shall be as specified in table II herein. Subgroups 5 and 6 in table I, method 5005

22、 of MIL-STD-883 shall be omitted. Subgroup 4 (GIN measurement) shall be measured only for the initial test and after process or design changes which may affect input capacitance. Subgroups 7 and 8 shall verify the functional operation of the device. manufacturers test tape and shall be maintained an

23、d available from approved sources of supply. Groups C and D inspections. End-point electrical parameters shall be as specified in table II herein. Steady-state life test conditions, method 1005 of MIL-STD-883. (1) Test condition A, B, C, or D using the circuit submitted with the certificate of compl

24、iance (see 3.6 herein). These tests form a part of the (2) TA = +12SoC, minimum. (3) Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883. STANDARDIZED MILITARY DRAWING SIZE A I DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 I REVISION LEVEL B 5962-87734 SHEET 7 3SC FO

25、RM 193A JUL 91 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-C - ARDY i FIGURE 1. Terminal connections. STANDARDIZED MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 I *.- SIZE 5962-87734 A REVISION LEVEL SHEET 8 B RES RESET II

26、 I SYNCHRONIZEH XI X2 EFI F/C XTAL . ose - 1 II CLK - SRDYEN - READY LOGIC - READY SRDY - A I- SI PCLK - J so - GENERATOF 4 PCLK - FIGURE 2. Logic diaqram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-vcc SIZE STANDARDIZED A MILITARY DRAWING 750 i

27、l 5962-87734 OUTPUT PCLK - “cc P 910n -L. 150 pF T - FIGURE 3. Output load. RESET, EFI drive and measurement points OTHER OUTPUT Co-I I CL T CLK output measurement points OUTPUT +.o v $1.0 v 2.4 v DEVICE INPUT 0.45 v DELAY +-j OTHER DEVI CE OUTPUT AC setup, hold and delay time measurements FIGURE 4.

28、 Switchinq waveforms. I DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 I REVISION LEVEL SHEET B I 9 I I I ESC FORM 193A JUL 91 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-87734 REV B 59 = 9999996 OOL24L7 2 ;1 ,. - CLK as a function

29、 of EFI EF I CLK OTE : The EFI input LOW and HIGH times as shown are required to guarantee the CLK LOW and HIGH times shown. RESET and READY timing as a function of RES with and 3 HIGH - BEADY IOTES: 1. 2. This is an asynchronous input. Tie 91On I5 percent pull-up resistor to the READY output. The s

30、etup and hold times shown are required to guarantee the response shown. - - READY and PCLK timing with RES HIGH CLK A- SI, so PCLK - SRDY t SRDY EN - ARIY ARDY EN READY - NOTES: 1. 2. This is an asynchronous input. Tie 910n i5 percent pull-up resistor to the READY output. The setup and hold times sh

31、own are required to guarantee the response shown. - FIGURE 4. Switchinq waveforms - Continued. SIZE 5962-87734 STANDARDIZED A MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER REVISION LEVEL SHEET DAYTON, OHIO 45444 A io IESC FORM 193A JUL 91 Provided by IHSNot for ResaleNo reproduction or networki

32、ng permitted without license from IHS-,-,-B SMD-59b2-87734 REV B 59 m 6199999b 0012418 4 = SIZE A STANDARDIZED MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 TABLE II. Electrical test requirements. 5962-87734 REVISION LEVEL SHEET Subgroups I Interim electrical parameters t I F

33、inal electrical test parameters i I*, 2, 3, 7*, 8, 9, I Group A test requirements i 1, 2, 3, 4, 7, 8, 9, I (per method I I MIL-STD-883 test requirements I 5W5, table I) I (method 5004) I I (method 5004) I IO, I1 I (method 5005) I IO, 11 I I I I I Groups C and D end-point electrical parameters (metho

34、d 5005) * PDA applies to subgroups 1 and 7. 5. PACKAGING 5.1 Packaging requirements. 6. NOTES 6.1 The requirements for packaging shall be in accordance with MIL-M-38510. Intended use. Microcircuits conforming to this drawing are intended for use when military ipecifications do not exist and qualifie

35、d military devices that will perform the required function are iot available for OEM application. :his drawing has been qualified for listing on QPL-38510, the device specified herein will be nactivated and will not be used for new design. or all applications. :overed by a contractor-prepared specif

36、ication or drawing. rith the users of record for the individual documents. iccordance with MIL-STD-481 using DD Form 1693, Engineering Change Proposal (Short Form). ihen a system application requires configuration control and the applicable SMD. ind this list will be used for coordination and distri

37、bution of changes to the drawings. iicroelectronics devices (FSC 5962) should contact DESC-ECT, telephone (513) 296-6023. When a military specification exists and the product covered by The QPL-38510 product shall be the preferred item 6.2 Replaceability. 6.3 Configuration control of SMDs. Microcirc

38、uits covered by this drawing will replace the same generic device All proposed changes to existing SHDs will be coordinated This coordination will be accomplished in 6.4 Record of users. Military and industrial users shall inform Defense Electronics Supply Center DESC will maintain a record of users

39、 Users of drawings covering 6.5 Comments. Comments on this drawing should be directed to DESC-ECC, Dayton, Ohio 45444, or elephone (513) 296-8526. 6.6 Approved sources of supply. Approved sources of supply are listed in MIL-BUL-103. The vendors listed in IIL-BUL-103 have agreed to this drawing and a

40、 certificate of compliance (see 3.6 herein) has been submitted to and iccepted by DESC-ECC. DESC FORM 193A JUL 91 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARDIZED MILITARY DRAWING SOURCE APPROVAL BULLETIN DATE: 93-05-34 Approved sources o

41、f supply for SMD 5962-87734 are listed below for immediate acquisition only and shall be added to MIL-BUL-103 during the next revision. MIL-BUL-103 will be revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate of compliance has

42、 been submitted to and accepted by DESC-ECC. This bulletin is superseded by the next dated revision of MIL-BUL-103. I I Military drawing I Vendor I Vendor i part number I CAGE I similar part I I number I number I/ I I I 5962-8773401VX I 34649 I MD82C284-10/8 I 5962-8773402VX I 34649 I MD82C284-8/B I

43、 5962-8773403VX I 34649 I MD82C284-6/8 I I I I l -I - I/ Caution. Do not use this number for item acquisition. may not satisfy the performance requireiaents of this drawing. Items acquired to this number Vendor CAGE number 34649 Vendor name and address Intel Corporation 3065 Bowers Avenue Santa Clar

44、a, CA 95051 Point of contact: SOM) West Chandler Boulevard Chandler, A2 85226 I l I The information contained herein is disseminated for convenience only and I I the Government assumes no Liability whatsoever for any inaccuracies in this 1 I information bulletin. I I Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-