DLA SMD-5962-87530 REV A-2011 MICROCIRCUIT MEMORY DIGITAL BIPOLAR PROGRAMMABLE LOGIC ARRAY MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Page 5 Table I, fMAX, change min. limit from 18 to 20 MHz; add to test (Minimum clock pulse width) tP(CL)LOW with a 30 ns min value; and modify Figure 4 accordingly. Boilerplate update, part of 5 year review. ksr 11-01-20 Charles F. Saffle THE OR

2、IGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED. REV SHET REV SHET REV STATUS REV A A A A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 PMIC N/A PREPARED BY Rick C. Officer DLA LAND AND MARITIME STANDARD MICROCIRCUIT DRAWING CHECKED BY Charles Reusing COLUMBUS, OHIO 43218-3990

3、 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael A. Frye MICROCIRCUIT, MEMORY, DIGITAL, BIPOLAR PROGRAMMABLE LOGIC ARRAY, MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 88-05-03 AMSC N/A REVISION LEVEL A SIZE A CAGE

4、CODE 67268 5962-87530 SHEET 1 OF 13 DSCC FORM 2233 APR 97 5962-E162-11 .Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87530 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM

5、 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-87530 01 K_ A Dra

6、wing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 PAL20S10 20-input, 10-output AND-OR Gate array with Product Term Sharing 02 PAL20RS10 20

7、-input, 10-output Registered AND-OR Gate array with Product Term Sharing 03 PAL20RS8 20-input, 8-output Registered AND-OR Gate array with Product Term Sharing 04 PAL20RS4 20-input, 4-output Registered AND-OR Gate array with Product Term Sharing 1.2.2 Case outline(s). The case outline(s) are as desig

8、nated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style K GDFP2-F24 or CDFP3-F24 24 Flat package L GDIP3-T24 or CDIP4-T24 24 Dual-in-line3 CQCC1-N28 28 Leadless chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1

9、.3 Absolute maximum ratings. 1/ Supply voltage range - -0.5 V dc to +7.0 V dc Storage temperature range - -65C to +150C Maximum power dissipation (PD) 2/ - 1.3 W Lead temperature (soldering, 10 seconds) - 260C Junction temperature (TJ) - +175C Thermal resistance, junction-to-case (JC): Cases K, L, a

10、nd 3 - See MIL-STD-1835 Input voltage range - -1.5 V dc to +5.5 V dc Off-state output voltage, maximum - -0.5 V to +5.5 V 1.4 Recommended operating conditions. Supply voltage (VCC) - +4.5 V dc to +5.5 V dc Input high voltage (VIH) - 2.2 V dc minimum Input low voltage (VIL) - 0.8 V dc maximum Case op

11、erating temperature range (TC) - -55C to +125C 1/ Unless otherwise specified, all voltages referenced to ground. 2/ Must withstand the added PDdue to short circuit test (e.g., IOS). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUI

12、T DRAWING SIZE A 5962-87530 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent s

13、pecified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Sta

14、ndard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.m

15、il/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in

16、this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. P

17、roduct built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan a

18、nd qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN

19、 as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A a

20、nd herein. 3.2.1 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.2 Truth table. The truth table shall be as specified on figure 2. 3.2.2.1 Unprogrammed devices. The truth table for unprogrammed devices for contracts involving no altered item drawing shall be as

21、specified on figure 2. When required in groups A, B, or C (see 4.3.1c), the devices shall be programmed by the manufacturer prior to test in a checkerboard pattern (a minimum of 50 percent of the total number of gates programmed) or to any altered item drawing pattern which includes at least 25 perc

22、ent of the total number of gates programmed. 3.2.2.2 Programmed devices. The truth tables for programmed devices shall be as specified by an attached altered item drawing. 3.2.3 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.3 Electrical performance characteristics. Unl

23、ess otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests

24、 for each subgroup are described in table I. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87530 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 4 DSCC FORM 2234 APR 97 TABLE I. Elect

25、rical performance characteristics. Test Symbol Conditions 1/ -55C TC+125C Group A subgroups Device type Limits Unit Min Max Input clamp voltage VICVCC= 4.5 V, II= -18 mA, 1, 2, 3 All -1.5 V High-level output voltage VOHVCC= 4.5 V, IO= -2.0 mA, 1, 2, 3 All 2.4 V IN= 0.8 V or 2.0 V Low-level output vo

26、ltage VOLVCC= 4.5 V; IOL= 12.0 mA VIL= 0.8 V, VIH= 2.0 V 1, 2, 3 All 0.5 V High-level Input current IIHVIH= 2.4 V, VCC= 5.5 V 2/ 1, 2, 3 All 25 A Low-level Input current IILVIL= 0.4 V, VCC= 5.5 V 2/ 1, 2, 3 All -0.25 mA Maximum input current IIVI= 5.5 V, VCC= 5.5 V 1, 2, 3 All 1 mA Output short circ

27、uit IOSVCC= 5.5 V, VO= 0.5 V VIL 0.8 V, VIH 2.0 V 1, 2, 3 All -30 -130 mA current 3/ Supply current ICCVCC= 5.5 V 1, 2, 3 All 240 mA Output leakage current IOZLVO= 0.4 V, VCC= 5.5 V 2/ VIL 0.8 V, VIH 2.0 V 1, 2, 3 All -100 A IOZHVO= 2.4 V, VCC= 5.5 V 2/ VIL 0.8 V, VIH 2.0 V 1, 2, 3 All 100 A Clock t

28、o output or feedback tCLKR1= 390 , R2= 750 VIL = 0 V, VIH= 3 V CL= 50 pF See figures 3 and 4 9, 10, 11 02,03, 04 20 ns Propagation delay high impedance to output high (OE to output enabled) tPZH9, 10, 11 02,03, 04 25 ns Propagation delay high impedance to output low (OE to output enabled) tPZL9, 10,

29、 11 02,03, 04 25 ns Propagation delay output high to high impedance (OE to output disabled) 4/ tPHZSee figures 3 and 4 9, 10, 11 02,03, 04 25 ns Propagation delay output low to high impedance (OE to output disabled) 4/ tPLZ9, 10, 11 02,03, 04 25 ns Propagation delay high impedance to output high tPZ

30、HSee figures 3 and 4 CL= 50 pF 9, 10, 11 01,03, 04 35 ns Propagation delay high impedance to output low tPZL9, 10, 11 01,03, 04 35 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A

31、5962-87530 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions 1/ -55C TC+125C Group A subgroups Device type Limits Unit Min Max Propagation delay output high to high impeda

32、nce. 4/ tPHZSee figures 3 and 4 9, 10, 11 01,03, 04 30 ns Propagation delay output low to high impedance 4/ tPLZ9, 10, 11 01,03, 04 30 ns Maximum frequency (Data path register) 5/ fMAXSee figures 3 and 4 CL= 50 pF 9, 10, 11 02,03, 04 20 MHz Propagation delay input to output. tPLHtPHLSee figures 3 an

33、d 4 CL= 50 pF 9, 10, 11 01,03, 04 40 ns fuse intact tPLHtPHL9, 10, 11 01,03, 04 45 ns fuse blown Minimum clock pulse width 5/ tP(CL) HIGH9, 10, 11 02,03, 04 20 ns tP(CL) LOW30Minimum setup time 5/ tSU9, 10, 11 02,03, 04 40 ns Minimum hold time 5/ tH9, 10, 11 02,03, 04 0 ns 1/ Unless otherwise specif

34、ied VCCis 4.5 V to 5.5 V. 2/ I/O terminal leakage is the worst case of IIXor IOZX. 3/ Only one output shorted at a time. 4/ CL= 5pF. 5/ Tested only initially and after any design changes. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PI

35、N listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance

36、 indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance.

37、A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply shall affirm that the manufac

38、turers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change

39、. Notification of change to DLA Land and Maritime-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DLA Land and Maritime, DLA Land and Maritimes agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required

40、 documentation. Offshore documentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87530 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVI

41、SION LEVEL A SHEET 6 DSCC FORM 2234 APR 97 Device types 01 02 03 04 Case outlines K and L 3 K and L 3 K and L 3 K and L 3 Terminal number Terminal symbol Terminal symbol Terminal symbol Terminal symbol Terminal symbol Terminal symbol Terminal symbol Terminal symbol 1 I0I0CLK CLK CLK CLK CLK CLK 2 I1

42、I1I0I0I0I0I0I03 I2I2I1I1I1I1I1I14 I3NC I2NC I2NC I2NC 5 I4I3I3I2I3I2I3I26 I5I4I4I3I4I3I4I37 I6I5I5I4I5I4I5I48 I7I6I6I5I6I5I6I59 I8I7I7I6I7I6I7I610 I9I8I8I7I8I7I8I711 I10NC I9NC I9NC I9NC 12 GND I9GND I8GND I8GND I813 I11I10OE I9OE I9OE I914 O0GND O0GND I/O0GND I/O0GND 15 I/O1I11O1OE O1OE I/O1OE 16 I

43、/O2O0O2O0O2I/O0I/O2I/O017 I/O3I/O1O3O1O3O1O3I/O118 I/O4NC O4NC O4NC O4NC 19 I/O5I/O2O5O2O5O2O5I/O220 I/O6I/O3O6O3O6O3O6O321 I/O7I/O4O7O4O7O4I/O7O422 I/O8I/O5O8O5O8O5I/O8O523 O9I/O6O9O6I/O9O6I/O9O624 VCCI/O7VCCO7VCCO7VCCI/O725 - NC - NC - NC - NC 26 - I/O8- O8- O8- I/O827 - O9- O9- I/O9- I/O928 - VCC

44、- VCC- VCC- VCCFIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87530 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 7 DSCC FORM 2234 APR 97 NOTE: X = lo

45、gic “dont care” state, Z = logic “high impedance” state, H = logic “high” state, and L = logic “low” state FIGURE 2. Truth tables (unprogrammed). Device type CLK OE I0I1I2I3I4I5I6I7I8I9I10I1101 - - X X X X X X X X X X X X 02 CLK L X X X X X X X X X X - - 03 CLK L X X X X X X X X X X - - 04 CLK L X X

46、 X X X X X X X X - - Device type O0O1O2O3O4O5O6O7O8O9O1001 Z Z Z Z Z Z Z Z Z Z - 02 H H H H H H H H H H - 03 Z H H H H H H H H H - 04 Z Z Z H H H H H Z Z - Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-8753

47、0 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 8 DSCC FORM 2234 APR 97 Test output loads Device type R1(ohms) R2(ohms) 01 - 04 390 ( 5%) 750 ( 5%) NOTE: Capacitors may be used to bypass VCCduring testing. FIGURE 3. Switching times test circuit. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZ