DLA SMD-5962-87527-1987 MICROCIRCUITS MONOLITHIC N-CHANNEL SILICON GATE SERIAL COMMUNICATION CONTROLLER《系列交流控制器单块N沟道硅口微型电路》.pdf
《DLA SMD-5962-87527-1987 MICROCIRCUITS MONOLITHIC N-CHANNEL SILICON GATE SERIAL COMMUNICATION CONTROLLER《系列交流控制器单块N沟道硅口微型电路》.pdf》由会员分享,可在线阅读,更多相关《DLA SMD-5962-87527-1987 MICROCIRCUITS MONOLITHIC N-CHANNEL SILICON GATE SERIAL COMMUNICATION CONTROLLER《系列交流控制器单块N沟道硅口微型电路》.pdf(23页珍藏版)》请在麦多课文档分享上搜索。
1、OF PAGES Defense Electronics Supply Center Dayton, Ohio Original date of drawing: 2 Apr 1 1987 AMSC NIA MILITARY DRAWING I This drawing is available for use by all Departments and Agencies of the Department of Defense TITLE: MICROCIRCUITS, MONOLITHIC BY N-CHANNEL SILICON GATE, SERIAL COMMUNICATION C
2、ONTROLLER 5962-87527 SIZE CODE IDENT. NO. DWG NO. A 14933 REV PAGE 1 OF 23 I I 5962-E284 DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited. DESC FORM 193 MAY 86 Licensed by Information Handling Services1, SCOPE 1.1 SCO e. This drawing describes device requirements for
3、class B microcircuits in accordance with 2,1 o to PCLK + -ITSIA(PC) I setup time I I setup time - I I hold time -1 I setup time - 1 I I I I INTACK to WR f 2/4/ ITsIAi (WR) I rNTACK to IR+ 2/1ThIA(WR) I INTACK to RD .L 2/4/ ITsIAi (RD) i I INTACK to RO .f 3/iThIA(RD) i hold time -1 I TRTXK to PCLK +
4、g/lThIA(PC) i hold time I I 19, 10, 11 I 19, 10, 11 7ioi io -+I- 8 180 I l 80 Max I 2000 I ns - 2/ i I 20 I ns 2/ I -1 I 20 I ns 2/ I -1 I 4000 I ns - 2/ I I ns I 19, 10, ill 9 I o I I ns I I I I I I I I I I 19, 10, ill 10 I o I IO1 I ns I I I I I I I I I I I I I ns 19, 10, 111 11 I 160 I I I I I I
5、I I I I I I I 19, 10, ill 12 I o I IO1 I ns I I I I I I I I .L i 19, 10, ill 13 I 160 I I 200 I I I I I I I I I I I I I Z/lThIA(RD) I 19, 10, 111 14 I O I IO1 I ns I I I I I I I I I I I l I I I I I I I I g/IThIA(PC) I 19, 10, 111 15 I 100 I I 100 I I ns I I I I I I I I I I I I See footnotes at end o
6、f table. I SIZE I CODE IDENT. NO. i DWG NO. I I I DESC FORM 193A FEB 86 Licensed by Information Handling ServicesLicensed by Information Handling Services, DESC-DWG-87527 57 7777775 0008623 5 -+ 7 - TABLE I. Electrical performance characteristics - Continued. I I I I I I I I Conditions IGroup A IRef
7、er-l Devi ce types I ivcc = 5.0 v-*lO% I I no. I I l I I I unless otherwise I I I Min I Max I Min I Max I I I specified I I I I I l l I I I I I I I I WRITE data to 2/1TsDW(WR) ISee figure 3, 19, 10, ill 29 I o I IO1 WR + setup time- I Iread and write, I I I I I I I linterrupt, reset, 1 I I I I WRITE
8、 data to IThDW(WR1 land cycle timings. 19, 10, 111 30 I O I IO1 I ns FTR + hold time I ICL = 50 PF *lo% I I I I I I I - I lunless otherwise 1 I I I kR + to wait 2/6/ITdWR(W) Ispecified 19, 10, 111 31 I I 200 I I 240 I ns valid delay - I I I I I I I I I 4 to wait 2/6/ITdRD(W) I 19, 10, ill 32 I I 200
9、 I I 240 I ns valid delay - I I I I I I I l I I I I I I + to wm 2/1TdWRf(REQ) I 19, 10, 111 33 I I 200 I I 240 I ns not valid delay- I I I I I I I I I I 240 I ns not valid delay- I I I I I l5TcPC I I5TcPC I ns not val id 2/ I I I I I delay -1 I I I I I I I I I RD 1. to m/m ITdRDr(REQ1 I 19, 10, 111
10、36 I I5TcPC i I5TcPC I ns not valid 2/ I I I I I It250 I del ay -1 I I I I I I I I I I I PCLK to INT 2/6/1TdPC(INT) 1 19, 10, ill 37 I I 500 I I 500 I ns valid delay - I I I I I I I I I I I I I (acknowledge)- I I I I delay I I I I I I width I I I I I I I I Test 1 Symbol I-55“C Tc +125Clsubgroupsl en
11、ce I -01 I -02 lUni t I - I I I I I I I I I 1 f I I I 250 I I I 250 I C to w/m 2/1TdRDf(REQ)I 19, 10, ill 34 I l to m, fTdWRr(REQ)i 19, 10, ill 35 I I I I I I - I I I INTACK to RD c 2/l/ITdIAi(RD) I RTJ (acknowledge) g/ITwRDA I 19, 10, 111 39 I 250 I I 285 I I I I I 19, 10, ill 38 I I I 1 ns RD + (a
12、cknowledge) ITdRDA(DR1 I 19, 10, ill 40 I I 180 I I 190 I ns - to read data I I I I I I I I z/ i val id delay I I I I I I I I I l I I IEI to + 2/1TsIEI(RDA)I 19, 10, 111 41 I 100 I I 120 I I ns (acknowledye) - I I I I I I I I I I setup time I I I I I I I I I I I I IEI to RD + Z/IThIEI(RDA)I 19, 10,
13、111 42 I O I IO1 I ns (acknowledge) - I I I I I I I I I I I hold time I I I I I I I See footnotes at end of table. SIZE CODE IDENT. NO. MILITARY DRAWING A 14933 DWG NO. 5963-87577 DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO REV PAGE 7 Licensed by Information Handling ServicesTABLE 1. Electrical p
14、erformance characteristics - Continued. I I I I t I SIZE MI LlTARY DR -0; ;Unit ivcc = 5.0 V-*lO% I I I unless otherwise I I I Min I Max I Min I Max I CODE IDENT. NO. DWG NO. 14933 5962-87527 I I specified 1 I 1 I I I ! I 120 I ns LEI to IEO 2/lfdIEI(IEO) ISee figure 3, 19, 10, ill 43 I delay time -
15、 I Iread and write, I I I I rinterrupt, reset, 1 I I I PCLK 4 to IEO ITdPC(IE0) land cycle timings. 19, 10, 111 44 I I 250 I i 250 I ns 2/ I ICL = 50 pF *lo% I I I I I lunless otherwise I I I I I delay I I -spec! fied I 500 I ns I RD J. to INT 2/6/iTdRA(INT) I 19, 10, 111 45 1 i 500 I inactive dela-
16、 I I I I I I I I I I I RD 4 to J. L/iTdRD(WRQ) i 19, 10, 1.11 46 I 15 I I 30 I I ns delay for no I I I I I I I I I reset I f I I I I I delay for no - I I I I I I I I reset I I I I I I I R and Rb I TwRES I 19, 10, 111 48 I 250 I 1 250 I I ns I I I I I I I coincident low I I I I I I For reset I I l I
17、I I I I I I recovery time - I I I I I I I I I I I I I I I I I I loo I I I I I -1 I -+-+ I I - I I I I l I i+130 I I I l I I Ispecified I I I I I I I I ns 4 to J. 2/lTdWRQ(RD) I 19, 10, ill 47 I 30 I I 30 I Val id access 2/8/ ITrC I 19, 10, 111 49 I6TcPC I I6TcPC I I ns PCLK !to g/m2J/TdPC(REQ) !See
18、figure 3, 19, 10, 111 1 I I 250 1 l 250 I ns -unless otherwise I PCLK +to wait g/ITdPC(W) RxC 4 to PCLK 4 ITsRXCPC) I 19, 10, 111 3 1 70 ITwPC1 1 80 ITwPC1 1 ns I I lyeneral timing. I I I I I IC, = 50 pF *lo% I I I I valid delay 19, 10, ill 2 I I 350 I I 350 I ns inqctive delay I I setup time 9/10/1
19、 I I I I I g/ I I 2/ I I -1 I I (PCLK+ 4 case I I I I I I only 1 I i I l l I I I I I IxD to 4 2/9/iTsRXD(RXCr) i 19, 10, ill 4 I o I Io1 I ns setup time - I I I I I I I I I (Xi mode) I I I I I I I I I I RxD to RxC 4 9/iThRXD(RXCr)i 19, 10, 111 5 i 150 1 1 150 I I ns I I hold time (Xi mode) I I I I I
20、 I RxD to J. 2/9/1TsRXR(RXCf) I 19, 10, ill 6 I O I IO1 setup time -g/l I I I I I I (Xi mode) I I I I I I I I I “I I I I I I I g I i I I I I I I ns I I See footnotes at end of table. DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO REV PAGE 8 Licensed by Information Handling ServicesTest SIZE CODE IDE
21、NT. NO. A 14933 MILITARY DRAW1 NG RxD to RxiT + hold time 9/11/ (Xi mode) - DWG NO. 5967-87577 - SYNC to 1. setup time SYNC to RxC 1. 2/91 hold time - DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO - TxC G to PCLK 1. REV PAGE g setup 10/12/ ti me _. TxC C to TxD delay (Xi mode) E/ - TxC 4 to TxD del
22、ay (Xi mode) 11/12/ - TxD to TRxC 21 delay (send - clock echo) RTX high width - 2/13/ - RTxC low width - U131 - RTxC cycle time - U131 Crystal 2/14/ oscillator - - period mC high width - U131 EC low width - 2/13/ TABLE I. Electrical performance characteristics - Continued. I I I I I I Unit I I I i C
23、onditions Group A Refer- Devi ce types IVIT = 5.0 W10% I I no. I Symbol I-55C TC +125“Clsubgroupsl ence I -01 -02 I unless otherwise I I I Min I Max I Min I Max I I I I I I I specified I I I l I I ThRXDRXCf 1 iSee figure 3, laeneral timina. CL = 50 pF *li)% Tunless otherwise TsSY (RXC 1 Ispeci fied
24、I I ThSYRXC) I I 1 TsTXC(PC) I I I I TdTXCf (TXD) I I I 7 TdTXCdTXD) I I I 1 TdTXD(TRX1 I I TwRTXh i I I 1 TwRTX1 I I I TcRTX I I I 1 I I I TwTRXh I I I I TwTRXl I I TcRTXX I 19, 10, ill 7 I 150 I I 150 I I ns I I I I I I I I I I I I I I 21 I I I ns 9, 10, 111 9 I3TcPC I I3TcPC I I ns I I I I I I 19
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