DLA SMD-5962-86053 REV G-2006 MICROCIRCUITS DIGITAL MEMORY BIPOLAR PROGRAMMABLE LOGIC MONOLITHIC SILICON《硅单块 双极可编程序逻辑 主储存器数字微型电路》.pdf

《DLA SMD-5962-86053 REV G-2006 MICROCIRCUITS DIGITAL MEMORY BIPOLAR PROGRAMMABLE LOGIC MONOLITHIC SILICON《硅单块 双极可编程序逻辑 主储存器数字微型电路》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-86053 REV G-2006 MICROCIRCUITS DIGITAL MEMORY BIPOLAR PROGRAMMABLE LOGIC MONOLITHIC SILICON《硅单块 双极可编程序逻辑 主储存器数字微型电路》.pdf（14页珍藏版）》请在麦多课文档分享上搜索。

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED D Add device type 05 to the drawing for vendor CAGE 34335. Add vendor CAGE 01295 for device type 04LX, 043X, and 04KX. Add footnote 9 to table I, subgroups 9, 10, and 11 testing. Changes to vendor similar part number for vendor CAGE 01295. Correcti

2、on to table I, parameter IOS. Editorial changes throughout. 91-05-01 M. A. Frye E Changes in accordance with NOR 5962-R298-97. 97-05-16 Raymond Monnin F Update drawing to current requirements. Editorial changes throughout. - gap 02-01-03 Raymond Monnin G Boilerplate update, part of 5 year review. ks

3、r 06-05-22 Raymond Monnin This original first sheet of this drawing has been replaced. CURRENT CAGE CODE 67268 REV SHET REV SHET REV STATUS REV G G G G G G G G G G G G OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/A PREPARED BY Greg A. Pitz STANDARD MICROCIRCUIT DRAWING CHECKED BY Dan DiCenzo DE

4、FENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Robert P. Evans AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 86-07-10 MICROCIRCUITS, DIGITAL, MEMORY, BIPOLAR PROGRAMMABLE LOGIC, MONOLITH

5、IC SILICON AMSC N/A REVISION LEVEL G SIZE A CAGE CODE 14933 5962-86053 SHEET 1 OF 12 DSCC FORM 2233 APR 97 5962-E450-06 .Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86053 DEFENSE SUPPLY CENTER COLUMBUS CO

6、LUMBUS, OHIO 43218-3990 REVISION LEVEL G SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is

7、 as shown in the following example: 5962-86053 01 K X Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 PAL22V10A 22-input 10-output re

8、gistered AND-OR logic array 02 PAL22V10 22-input 10-output registered AND-OR logic array 03 PAL22VP10-25 22-input 10-output registered AND-OR logic array 04 PAL22V10-20 22-input 10-output registered AND-OR logic array 05 PAL22V10-12 22-input 10-output registered AND-OR logic array 1.2.2 Case outline

9、(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style K GDFP2-F24 or CDFP3-F24 24 Flat package L GDIP3-T24 or CDIP4-T24 24 Dual-in-line 3 CQCC1-N28 28 Leadless chip carrier 1.2.3 Lead finish. The lead finish is as spe

10、cified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. 1/ Supply voltage range. -0.5 V dc to +7.0 V dc Input voltage range . -0.5 V dc to +5.5 V dc Output voltage applied -0.5 V dc to +7.0 V dc 2/ Output sink current +100 mA 2/ Thermal resistance, junction-to-case (JC): Cases K, L, and 3

11、 See MIL-STD-1835 Maximum power dissipation (PD) 3/ 1.2 W Maximum junction temperature . +175C Lead temperature (soldering, 10 seconds maximum) +260C 1.4 Recommended operating conditions. Supply voltage (VCC) . 4.5 V dc to 5.5 V dc High level input voltage (VIH). 2.0 V dc minimum Low level input vol

12、tage (VIL) 0.8 V dc maximum _ 1/ All voltages referenced to VSS. 2/ Except during programming. 3/ Must withstand the added PDdue to short circuit test; e.g., IOS. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 59

13、62-86053 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL G SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified h

14、erein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Micr

15、ocircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksea

16、rch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes prece

17、dence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as s

18、pecified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers appro

19、ved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall

20、not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-3

21、8535, appendix A and herein. 3.2. Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2. Terminal connections. The terminal connections shall be as specified on figure 1. 3.2. Truth tables. 3.2.3.1 Unprogrammed devices. The truth table for unprogrammed devices for contracts

22、involving no altered item drawing shall be as specified on figure 2. When required in groups A, B, or C (see 4.4), the devices shall be programmed by the manufacturer prior to test with a minimum of 50 percent of the total number of gates programmed) or to any altered item drawing pattern which incl

23、udes at least 25 percent of the total number of gates programmed. 3.2.3.2 Programmed devices. The truth table for programmed devices shall be as specified by an attached altered item drawing. 3.2. Logic diagram. The logic diagram shall be as specified on figure 3. 3.3 Electrical performance characte

24、ristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT D

25、RAWING SIZE A 5962-86053 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL G SHEET 4 DSCC FORM 2234 APR 97 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in ta

26、ble I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the

27、manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certificat

28、ion mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of complian

29、ce submitted to DSCC-VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A

30、shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DSCC-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DSCC, DSCCs agent, and the acquiring activity retain the option to review

31、 the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Processing options. Since the device is capable of being programmed by either the manufacturer or the user to result in a wide variety of conf

32、igurations, two processing options are provided for selection in the contract, using an altered item drawing. 3.10.1 Unprogrammed device delivered to the user. All testing shall be verified through group A testing as defined in 3.2.3.1 and table II. It is recommended that users perform subgroups 7 a

33、nd 9 after programming to verify the specific program configuration. 3.10.2 Manufacturer-programmed device delivered to the user. All testing requirements and quality assurance provisions herein, including the requirements of the altered item drawing, shall be satisfied by the manufacturer prior to

34、delivery. 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspect

35、ion. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition C or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request.

36、The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. (2) TA= +125C, minimum. b. Interim and final electrical test parameters shall be as specified in table II herein, except interim el

37、ectrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86053 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REV

38、ISION LEVEL G SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ -55C TC +125C unless otherwise specified Group A subgroups Device type Limits Unit Min MaxInput clamp voltage VICVCC= 4.5 V, II= -18 mA 1, 2, 3 All -1.2 V High level output VOHIO= -

39、2.0 mA, VCC= 4.5 V, 1, 2, 3 All 2.4 V voltage VIN= 2.0 V or 0.8 V Low level output VOLIO= 12.0 mA, VCC= 4.5 V, 1, 2, 3 All 0.5 V voltage VIN= 2.0 V or 0.8 V High impedance output IOZHVCC= 5.5 V, VO= 2.7 V 1, 2, 3 All 100 A leakage current 2/ IOZLVIN= VIHor VILVO= 0.4 V -100 High level input IIHVIN=

40、2.7 V, VCC= 5.5 V 1, 2, 3 All 25 A current VIN= 5.5 V, VCC= 5.5 V 1, 2, 3 All 1.0 mA Low level input IILVIN= 0.4 V, VCC= 5.5 V 1, 2, 3 All -250 A current Supply current ICCVCC= 5.5 V 1, 2, 3 02 180 mA 03 230 01, 04, 05 200 Output short circuit IOSVCC= 5.5 V, VO= 0.5 V 1, 2, 3 01, 02, -30 -90 mA curr

41、ent 3/ 03, 04 05 -30 -130 Propagation delay tPZDVCC= 5.0 V 10%, 9, 10, 11 01 30 ns output high CL= 50 pF 02 40 impedance to output See figures 4 and 5 4/ 03 25 valid 04 20 05 15 Propagation delay tPDZ9, 10, 11 01 30 ns output valid to 5/ 02 40 output high 03 25 impedance 04 20 05 12.5 See footnotes

42、at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86053 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL G SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance c

43、haracteristics - Continued. Test Symbol Conditions 1/ -55C TC +125C unless otherwise specified Group A subgroups Device type Limits Unit Min MaxPropagation delay 6/ tPHLVCC= 5.0 V 10%, 9, 10, 11 01 30 ns data input to output CL= 50 pF 02 40 See figures 4 and 5 4/ 03 25 04 20 05 12 Propagation delay

44、6/ tPLH9, 10, 11 01 30 ns data input to output 02 40 03 25 04 20 05 12 Clock pulse width 7/ tCL9, 10, 11 01,03 20 ns 02 30 04 15 05 6 Setup time 7/ tSU9, 10, 11 01,03 25 ns 02 35 04 17 05 10 Hold time 7/ tH9, 10, 11 All 0 ns Maximum clock fMAX9, 10, 11 01 22 MHz frequency 7/ 8/ 02 16.5 03 25 04 33.3

45、 05 50 Asynchronous reset tAW9, 10, 11 01,03 30 ns pulse width 7/ 9/ 02 40 04 20 05 15 Asynchronous reset tAR9, 10, 11 01,03 30 ns recovery time 7/ 9/ 02 40 04 20 05 10 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-ST

46、ANDARD MICROCIRCUIT DRAWING SIZE A 5962-86053 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL G SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics Continued. Test Symbol Conditions 1/ -55C TC +125C unless otherwise specified Group A subgroups Device

47、 type Limits Unit Min MaxAsynchronous reset to tAP4/ 9, 10, 11 01 35 ns registered output 02 45 reset 7/ 03, 04 25 05 20 Propagation delay tCO9, 10, 11 01 20 ns clock to output 7/ 02 25 03, 04 15 05 10 1/ All voltages are referenced to ground. 2/ I/O terminal leakage is the worst case of IIXor IOZ.

48、3/ Only one output shorted at a time. 4/ Equivalent test loads may be used for testing when submitted to and approved by DSCC. 5/ CL= 5 pF for tPDZtest. 6/ Test applies only to non-registered (combinational logic) outputs. 7/ Test applies only to register outputs. 8/ fMAXis derived by testing tSUand tCOand is not tested directly. 9/ Not tested directly, but guaranteed by testing of tAPand tSU. TABLE