DLA SMD-5962-86051 REV D-2011 MICROCIRCUIT MEMORY DIGITAL BIPOLAR 64-BIT RAM MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Update vendors part number. Change to military drawing format. Editorial changes throughout. 87-07-07 M. A. Frye B Made technical changes to table I. Added device types 07, 08, and 09 for vendor CAGE 34335. Changes to figures 4, 5, 6. Changes to

2、4.3.2 and 6.4. Corrected CAGE code on front page. Editorial changes throughout. 89-06-13 M. A. Frye C Boilerplate update, part of 5 year review. ksr 05-08-31 Raymond Monnin D Updated body of drawing to reflect current requirements. - glg11-03-08 Charles Saffle CURRENT CAGE CODE 67268 THE ORIGINAL FI

3、RST SHEET OF THIS DRAWING HAS BEEN REPLACED REV SHET REV SHET REV STATUS REV D D D D D D D D D D D D D OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 PMIC N/A PREPARED BY Sandra Rooney DLA LAND AND MARITIME STANDARD MICROCIRCUIT DRAWING CHECKED BY D. A. DiCenzo COLUMBUS, OHIO 43218-3990 http:/www.dsc

4、c.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Don Cool MICROCIRCUIT, MEMORY, DIGITAL, BIPOLAR 64-BIT RAM, MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 25 March 1986 AMSC N/A REVISION LEVEL D SIZE A CAGE CODE 14933 86051 SHEET 1 OF 13

5、 DSCC FORM 2233 APR 97 5962-E189-11 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 86051 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This dra

6、wing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 86051 01 E A Drawing number Device type (see 1.2.1) Case outlin

7、e(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit Access time 01 27S02 64-Bit Schottky bipolar RAM, open collector outputs 50 02 27S02A 64-Bit Schottky bipolar RAM, open collector outputs 30 03 27L

8、S02 64-Bit Low power schottky bipolar RAM, open collector 65 outputs 04 27S03 64-Bit Schottky bipolar RAM, three-state outputs 50 05 27S03A 64-Bit Schottky bipolar RAM, three-state outputs 30 06 27LS03 64-Bit Low power schottky bipolar RAM, three-state 65 outputs 07 27S02-20 64-Bit Schottky bipolar

9、RAM, open collector outputs 20 08 27S03-20 64-Bit Schottky bipolar RAM, three-state outputs 20 09 27LS03-30 64-Bit Low power Schottky bipolar RAM, three-state 30 outputs 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator

10、 Terminals Package style E GDIP1-T16 or CDIP2-T16 16 Dual-in-line package F GDFP2-F16 or CDFP3-F16 16 Flat package 2 CQCC1-N20 20 Square-chip carrier package 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Supply voltage range . -0.5 V d

11、c to +7.0 V dc Input voltage range -0.5 V dc to +5.5 V dc Storage temperature range -65C to +150C Maximum power dissipation (PD) 1/ . 1.6 W Lead temperature (soldering, 10 seconds) . +300C Thermal resistance, junction-to-case (JC): Cases E, F and 2 See MIL-STD-1835 Junction temperature (TJ) . +175C

12、DC input current -30 mA to +5 mA 1.4 Recommended operating conditions. Supply voltage range (VCC) 4.5 V dc minimum to 5.5 V dc maximum Minimum high-level input voltage (VIH) . 2.0 V dc Maximum low-level input voltage (VIL) 0.8 V dc Case operating temperature range (TC) . -55C to +125C 1/ Must withst

13、and the added PDdue to short circuit test (e.g., IOS). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 86051 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 3 DSCC FORM 2234 APR 97 2. APPLIC

14、ABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTME

15、NT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-

16、103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2

17、Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.

18、1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a ma

19、nufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan ma

20、y make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow o

21、ption is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.2 Truth table. The truth tabl

22、e shall be as specified on figure 2. 3.2.3 Logic diagram. The logic diagram shall be as specified on figure 3. 3.2.4 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance ch

23、aracteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Mar

24、king shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to

25、 MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD

26、MICROCIRCUIT DRAWING SIZE A 86051 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 4 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Group Limits Test Symbol Conditions A sub- Device Unit -55C TC +125C groups type 4.5 V dc VCC 5.5 V dc Min Max unless othe

27、rwise specified Output high voltage VOHVCC= min. 1,2,3 All 2.4 V VIN= VIH or VILIOH= -2.0 mA 01,02, Output low voltage VOLVCC= min. IOL= 16 mA 1,2,3 04,05, 450 mV VIN= VIH 07,08 or VILIOL= 20 mA 01,02, 500 04,05, 07,08 IOL= 10 mA 03,06, 500 09 IOL= 8 mA 03,06, 450 09 Input high level VIHGuaranteed i

28、nput logical high 1/ 1,2,3 All 2.0 V voltage voltage for all inputs Input low level VILGuaranteed input logical low 1/ 1,2,3 All 0.8 V voltage voltage for all inputs Input low current IILVCC= max WE , D0-D3, 1,2,3 All -250 A VIN= 0.40 V A0-A3, CS Input high current IIHVCC= max, VIN= 2.7 V 1,2,3 All

29、10 A Output short circuit IOSVCC= max 1,2,3 All -20 -90 mA current VOUT= 0.0 V 2/ 01,02, Power supply current ICCAll inputs = GND 1,2,3 04,05, 105 mA VCC= max 07,08 03,06 38 09 Input clamp voltage VCLVCC= min, IIN= -18 mA 1,2,3 All -1.2 V See footnotes at end of table. Provided by IHSNot for ResaleN

30、o reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 86051 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Group Limits Test Symbol Conditio

31、ns A sub- Device Unit -55C TC +125C groups type 4.5 V dc VCC 5.5 V dc Min Max unless otherwise specified Output leakage current ICEXVCS% = VIHor VWE$ $ $ = VIL1,2,3 All 40 A VOUT= 2.4 V VCS% = VIHor VWE$ $ $ = VIL All -40 VOUT= 0.4 V Delay from address to tPLH(A)See figures 4 and 6 3/ 9,10,11 01,04

32、50 ns output tPHL(A) 02,05 30 09 03,06 65 07,08 20 Delay from chip select tPZH(CS%) See figures 4 and 6 4/ 5/ 9,10,11 01,04 25 ns (LOW) to active out- tPZL(CS%) 02,05, 20 put and correct data 07,08, 09 03,06 35 Delay from write enable tPZH(WE$ $ $) See figures 4 and 5 4/ 5/ 9,10,11 01,04 40 ns (HIGH

33、) to active out- tPZL(WE$ $ $) 02,05 25 put and correct data 03,06 35 (write recovery) 6/ 07,08, 15 09 Setup time address ts(A)See figures 4 and 5 9,10,11 All 0 ns (prior to initiation of write) Hold time address th(A)See figures 4 and 5 9,10,11 All 0 ns (after termination of write) 09 30 Setup time

34、 data input ts(DI)See figures 4 and 5 9,10,11 01,02, 25 ns (prior to termination 04,05 of write) 03,06 55 07,08 20 Hold time data input th(DI)See figures 4 and 5 9,10,11 All 0 ns (after termination of write) See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking pe

35、rmitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 86051 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Group Limits Test Symbol Conditions A sub- Device Unit -55C TC +

36、125C groups type 4.5 V dc VCC 5.5 V dc Min Max unless otherwise specified 09 30 Min write enable pulse tpw(WE$ $ $)See figures 4 and 5 9,10,11 01,02, 25 ns width to insure write 04,05 03,06 55 07,08 20 Delay from chip select tPHZ(CS%)See figures 4 and 6 4/ 5/ 9,10,11 01,04, 25 (HIGH) to inactive tPL

37、Z(CS%) 09 output (HI-Z) 02,05, 20 ns 07,08 03,06 35 Delay from write enable tPLZ(WE$ $ $) See figures 4 and 5 4/ 5/ 9,10,11 01,03, 35 ns (LOW) to inactive tPHZ(WE$ $ $) 04,06 output (HI-Z) 02,05, 25 09 07,08 20 1/ These are absolute voltages with respect to device ground pin and include all overshoo

38、ts due to system and/or tester noise. Do not attempt to test these values without suitable equipment. 2/ Not more than one output should be shorted at a time. Duration of the short circuit should not be more than one second. 3/ Parameters tPLH(A)and tPHL(A)are tested with S1 closed and CL = 30 pF wi

39、th both input and output timing referenced to 1.5 V. 4/ For open collector, all delays from Write Enable ( WE ) or Chip Select ( CS ) inputs to the Data Output (DOUT), tPLZ(WE$ $ $), tPLZ(CS%), tPZL(WE$ $ $), and tPZL(CS%)are measured with S1 closed and C1 = 30 pF; and with both the input and output

40、 timing referenced to 1.5 V. 5/ For 3-state output, tPZH(WE$ $ $)and tPZH(CS%)are measured with S1 open, CL = 30 pF and with both the input and output timing referenced to 1.5 V. Parameters tPZL(WE$ $ $)and tPZL(CS%)are measured with S1 closed, CL = 30 pF and with both the input and output timing re

41、ferenced to 1.5 V. Parameters tPHZ(WE$ $ $)and tPHZ(CS%)are measured with S1 open and CL 5 pF and are measured between the 1.5 V level on the input and the VOH= -500 mV level on the output. Parameters tPLZ(WE$ $ $)and tPLZ(CS%)are measured with S1 closed CL 5 pF and are measured between the 1.5 V level on the input and the VOL= +500 mV level on the output. 6/ Output is preconditioned to data in (inverted) during write to ensure correct data is presen