DLA SMD-5962-85518 REV A-1987 MICROCIRCUIT MONOLITHIC N-CHANNEL SILICON GATE SERIAL COMMUNICATIONS CONTROLLER《系列交流控制器 银门 N沟道 单块微型电路》.pdf

《DLA SMD-5962-85518 REV A-1987 MICROCIRCUIT MONOLITHIC N-CHANNEL SILICON GATE SERIAL COMMUNICATIONS CONTROLLER《系列交流控制器 银门 N沟道 单块微型电路》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-85518 REV A-1987 MICROCIRCUIT MONOLITHIC N-CHANNEL SILICON GATE SERIAL COMMUNICATIONS CONTROLLER《系列交流控制器 银门 N沟道 单块微型电路》.pdf（22页珍藏版）》请在麦多课文档分享上搜索。

1、- DESC-DWG-85518 REV A 57 m 7777775 0005001 T W REVISIONS LT R DESCRIPTION DATE APPROVED r JJ%JJ4 A Change drawing CAGE number to 67268 tiov si and add a vendor CAGE no. 66958. Editorial changes throughout. 1 SIZE A 16 July 1986 -. / -75- 37 .5962-85518 CODE IDENT- NO. OW NO. 14333 REV A AMSC NIA CU

2、RRENT CAGE CODE 67268 PAOE 1 OF . 22 Defense Electronics I P EPARED % , I. BY -. 1 MILITARY DRAWING Supply Center Dayton, Ohio Original date of drawing: This drawing is available for use by all Departments and Agencies of the Depart- ment of Defense TITLE: MICROCIRCUIT, MONOLITHIC, COMFIUII ICAT I O

3、N S CONTROLLER N-CHANNEL, SILICON GATE, SERIAL 5962-E604 DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited. DESC FORM 193 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,- - - DESC-DWG-55l REV A 59 M 7777775 0005002 1i W

4、 1. SCOPE 1.1 SCO e. This drawing describes device requirements for class 6 microcircuits in accordanc with .2.1 o?emperature ranye. 3.4 Markin . Marking shall be in accordance with MIL-STU-883 (see 3.1 herein). The part shall be larked de part number listed in 1.2 herein. In addition, the manufactu

5、rers part number may also le marked as listed in 6.5 herein. 4-. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-TABLE I. Electrical performance characteristics. MILITARY DRAWING I I Test ISymbol I Conditions I -55C 5 TC lu t I n(“-, yo- I-. Provided

6、 by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DESC-DWG-85518 REV A 57 W 7777775 00050L4 8 SIZE A Device types O1 and 02 DWG NO. 5962- 85510 READ AND WRITE TIMING REV AC CSO CS I PAGE 14 INTACK R/ w R /v READ WRITE -7 - OS ADo-AD WRITE ADO- AD7 READ -.- W/

7、RE Q WAIT -I_ W/RE Q REQUEST DTR/REQ REQUEST I NT *I Il- P.1 * I, 7 f FIGURE 3. Timing diagram. MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO DESC FORM 193A FEB 86 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DESC-DWG-45514 REV A

8、 57 m 9777795 00050L5 T m + Device types U1 and 02 INTERRUPT ACKNOWLEDGE TIMING INTACK ADO- AD7 IE I IE O INT RESET TIMING v- h I CYCLE TIMING - A- PCLK FIGURE 3. Timing dia- Continued. MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO DESC FORM 193A DWG NO. SIZE 5962-85518 A REV PAGE

9、15 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DESC-DWG-85518 REV A 57 7777775 00050Lb I M SIZE MILITARY DRAWING A Device types U1 and 02 DWG NO. 5062-85518 GENERAL TIMING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO PCLK REV PAGE 16 W/REQ REQU

10、E ST W/REQ WAIT 7- RTx C, TRx C RECEIVE Rx D - SYNC EXTERNAL _I- TRxC, RTxC TRANSMIT Tx D CI TR XC OUTPUT RTxC P P TRxC -I_ CTC ,DCD _. CY NC INPUT FIGURE 3. Timing diagram - Continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DESC-DWG-85518 R

11、EV A 57 7777795 00050L7 3 W SIZE MILITARY DRAWING A Device types U1 and 02 DWG NO. 5962-85518 SYSTEM TIMING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO - RT x C, TR x C RECE I VE I I REV PAGE 17 W/REQ REQUEST W/REQ WAIT SYNC OUTPUT INT - RT xC, TRx C TRANS M IT W/REQ REQUEST W/REQ WAIT DTR/REQ RE

12、QUEST I * 4 I f + INT - CTC, DCD SYNC INPUT INT FIGURE 3. Timing diagram - Continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-3.5 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in rder to be liste

13、d as an approved source of supply in 6.5. The certificate of compliance submitted to ESC-ECS prior to listing as an approved source of supply shall state that the manufacturers product eets the requirements of MIL-STD-883 (see 3.1 herein) and the requirements herein. SIZE MILITARY DRAWING A 3.6 Cert

14、ificate of confonnance. A certificate of conformance as required in MIL-STD-883 (see 3.1 erein) shall be provided with each lot of microcircuits delivered to this drawing. DWG NO. 5962-85518 3.7 Notification of change. Notification of change to DESC-ECS shall be required in accordance with IL-STD-88

15、3 (see 3.1 herein). DEFENCE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 3.8 Verification and review, DESC, DESCs ayent, and the acquiring activity retain the option to evew the manufacturers facility and applicable required documentation. Offshore documentation shall e made available onshore at the optio

16、n of the reviewer. 4, QUALITY ASSURANCE PROVISIONS REV A PAGE 18 4.1 Sampl i ng and inspection. Sampl i ng and i nspection procedures chal 1 be i n accordance with section of MIL-M-38510 to the extent specified in MIL-STD-883 (see 3.1 herein). 4.2 Screenin , Screening shall be in accordance with met

17、hod 5004 of MIL-STD-883, and shall be onducte -a-+ on a devices prior to quality conformance inspection. The following additional criteria ,hall apply: a, Burn-in test (method 1015 of MIL-STD-883). (1) Test condition A, B, C, or D using the circuit submitted with the certificate of compliance (see 3

18、.5 herein). (2) TA = +125C, minimum. Interis and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. Wality conforinance inspection shall be in accordance with b. 4.3

19、 Quality conformance inspection. iethod a05 of MIL-STD-883 including groups A, B, C, and D inspections. The following additional riteria shall apply. 4.3.1 Group A inspection. a. Tests shall be as specified in table II herein, b. Subgroups 4, 5, and 6 in table I, methad 5005 of MIL-STD-883 shall be

20、omitted. c. Subgroup 7 tects shall include verification of the instruction set. 4.3.2 Groups C and D inspections. a. End-point electrical parameters shall be as specified in table II herein. b. Steady-state life test (method 1005 of MIL-STD-883) conditions: (1) Test condition A, B, C, or D using the

21、 circuit submitted with the certificate of compliance (see 3.5 herein). (2) TA = +125C, minimum. (31 Test duration: 1,000 hours, except as permitted by appendix B of MIL-M-38510 and method 1005 Of MIL-STD-883s e- Provided by IHSNot for ResaleNo reproduction or networking permitted without license fr

22、om IHS-,-,-DESC-DWG-5518 REV A 57 7777775 00050L7 7 W SIZE MILITARY DRAWING A TABLE II. Electrical test requirements. I I Subgroups I I MIL-STO-883 test requirements I (per inethod I I 5005, table I) I I I I I I Interim electrical parameters I I I I (method 5004) I I I IFinal electrical test paramet

23、ers I I I (method 5004) I 1*, 2, 3, 9 I I I I - DWG NO. 5962-85518 Group A test requirements I i I I (method 5005) I 1, 2, 3, 7, 8, 1 I I 9, 10, 11“ I Groups C and D end-point I I I (method 5005) I lelectrical parameters I 1s 2, 3 I I I DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO I I I I REV A PA

24、GE 19 * PDA applies to subyroup 1. * Subgroups 10 and 11, if not tested, shall be guaranteed to the specified limits in table I. 5. PACKAGING 5.1 Packaging requirements. 6. NOTES 6.1 Intended use. Microcircuits conforming to this drawiny are intended for use when military The requirements for packag

25、iny shall be in accordance with NIL-M-38510. pecifications do not exist and qualified military devices that will perform the required function are iot available for OEbi application. ,his drawing has been qualified for listing on QPL-38510, the device specified herein will be nactivated and will not

26、 be used for new design. 11 appl ications. When a military specification exists and the product covered by The QPL-38510 product shall be the preferred item for 6.2 Re laceability. Microcircuits covered by this drawing will replace the same generic device overed + y a contractor-prepared specificati

27、on or drawing. 6.3 Comments. Comments on this drawing should be directed to DESC-ECS, Dayton, Ohio 45444, or .elephone 513-296-5375. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-I SIZE MILITARY DRAWING A DESC-DWG-85514 REV AFI i-7777745 O005020 3

28、C DWG NO. 5962-85518 6.4 Symbol s, definitions, and functional descriptions. The symbols, definitions, and functional (The following section describes the pin functions of the I-SCC. Figures 1 and 2 detail the escriptions for these devices shall be as follows: espective pin functions and pin assignm

29、ents. 1 Ao-AD7. Addresddata bus (bidirectional, active high, 3-state). These mu1 tiplexed lines carry register addresses to the Z-SCC as well as data or control information to and from the Z-SCC. n. Address strobe (input, active low). Addresses on ADo-AD7are latched by the rising edge of thi s signa

30、l. EO, Chip select O (input, active low). This signal is latched concurrently with the addresses on ADo-AU7 and must be active for the intended bus transaction to occur. CS1. Chip select 1 (input, active high). This second select signal must also be active before the intended bus transaction can occ

31、ur, CS1 must remain active throughout the transaction. FTSK, m. Clear to send (inputs, active low), low on the inputs enables their respective transmitters. niay be used as general-purpose inputs. Both inputs are Schmitt-trigger buffered to accommodate slow rise-time inputs. The device detects pulse

32、s on these inputs and can interrupt the CPU on both 1 ogic 1 evel trdnsi tions, d, m. Data carrier detect (inputs active low). These pins function as receiver enables if they are programed for auto enables; otherwise they may be used as general-purpose input pins. Both pins are Schnitt-trigger buffe

33、red to accomnodate slow rise-time signals, The Z-SCC detects pulses on these pins and can interrupt the CPU on both logic level transitions. m. Data strobe (input, active low). This signal provides timing for the transfer of data into and out of the 2-SCC. If KS and 0s coincide, this is interpreted

34、as a reset. If these pins are programed as auto enables, a If not programned as auto enables, they oTR/RFQA, mm. Data teminal ready/request (outputs, active low), These outputs follow the state programed into the TR bit. They can also be used as general-purpose outputs or as request lines for a DMA

35、controller. IEI. chain when there is more than one interrupt-driven device. A high IEI indicates that no other higher priority device has an interrupt under service or is requesting an interrupt. Interrupt enable in (input, active high). IEI is used with IEO to form an interrupt daisy IEO, not servi

36、cing a I-SCC interrupt or the Z-SCC is not requesting an interrupt (interrupt acknowledge cycle only). IEO is connected to the next lower priority devices IEI input and thus inhibits interrupts from 1 ower priority devices. Interrupt enable out (output, active high), IEO is high only if IEI is high

37、and the CPU is m, Interrupt request (output, open-drain, active low). This signal is activated when the Z-SCC requests an interrupt. m. Interrupt acknowledge (input, active low). This signal indicates an active interrupt acknowlde e cycle. During this cycle, the Z-SCC interrupt daicy chain settles.

38、When 0: becomes active, tie Z-SCC plac- an interrupt vector on the data bus (if IEI is high). TKlXK is latched by the rising edge of AS. PCLK. Clock (input), This is the master Z-SCC clock used to synchronize internal signals, PCLK is not required to have any phase relationship with the master syste

39、m clock, although the frequency of this clock must be as least 90 percent of the CPU clock frequency for a 28000. PCLK i s a TTL level signal . RxDA, RxDB. Receive data (inputs, active high). These input signals receive serial data at standard TTL 1 evel s. DEFENSE ELECTRONICS SUPPLY CENTER I I PAGE

40、 20 DAYTON, OHIO REV A DESC FORM 193A FEE 86 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-6.4 Symbols, definitions, and functional descriptions - Continued. MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER RTZii, RTXCB. Receive/transmit clock (i

41、nputs, active lo& These pins can be programed in several different modes of operation. trdnsmit clock, the clock for the baud rate generator, or the clock of the digital phase-locked loop. These pins can also be programed for use with the respective SYNC pins as a crystal oscillator. The receive clo

42、ck may be 1, 16, 32, or 64 times the data rate in asynchronous modes. RTSA, RTS. Request to send (outputs, active low). When the request to send (RTS) bit in write register 5 is set, the RTs signal goes low. When the RTS bit is reset in the asynchronous mode and auto enable is on, the signal goes hi

43、gh after the transmitter is empty. In synchronous mode or in asynchronous mode with auto enable off, the TUS pin strictly follows the state of the RTS bit. Both pins can be used as general-purpose outputs. In each channel, RTxC may supply the receive clock, the A. 5962-85518 I I R/A, Read/write (inp

44、ut). This signal specifies whether the operation to be performed is a read or a write. m, SYNCE. Synchronization (inputs or outputs, active low). These pins can act either as inputs, outputs, or part of the crystal oscillator circuit. In the asyn%onousEeive mode (crystal oscillator option not select

45、ed), these pins are inputs similar to CTS and DCD. synchronouslhunt status bits in read register O but have no other function. In external synchronization mode with the crystal oscillator not selected, these lines also act as inputs. synchronous character is received. clock imediately preceding the

46、activation of m. In the internal synchronization mode (Monosync and bisync 1 with the crystal osci 11 ator not selected, these pins act as outputs and are active only duriny the part of the receive clock cycle in which synchronous characters are recognized. The synchronous condition is not latched,

47、so these outputs are active each time a synchronizdtion pattern is recognized (regardless of character boundaries). In SDLC mode, these pins act as outputs and are valid on receipt of a flag TxDA, TxD6. Transmit data (outputs, active high). These output signals transmit serial data at standard TTL l

48、evel s. m, m. Transmit/receive clocks (inputs or out uts, active low). These pins can be transmit clock in the input mode or supply the output of the digital phase-locked loop, the crystal oscillator, the baud rate generator, or the transmit clock in the output mode. WREVi, WRQlT. Wait/request (outp

49、uts, open-drain when programed for a wait function, driven high or low when programed for a request function). as request lines for a DMA controller or as wait lines to synchronize the CPU to the Z-SCC data rate. The reset state is wait. In this mode, transitions on these lines affect the state of the In this mode, 3YXmust be driven