DLA SMD-5962-85507 REV F-2009 MICROCIRCUIT DIGITAL HIGH-SPEED CMOS OCTAL D-TYPE FLIP-FLOP WITH THREE-STATE OUTPUTS TTL COMPATIBLE INPUTS MONOLITHIC SILICON.pdf

《DLA SMD-5962-85507 REV F-2009 MICROCIRCUIT DIGITAL HIGH-SPEED CMOS OCTAL D-TYPE FLIP-FLOP WITH THREE-STATE OUTPUTS TTL COMPATIBLE INPUTS MONOLITHIC SILICON.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-85507 REV F-2009 MICROCIRCUIT DIGITAL HIGH-SPEED CMOS OCTAL D-TYPE FLIP-FLOP WITH THREE-STATE OUTPUTS TTL COMPATIBLE INPUTS MONOLITHIC SILICON.pdf（14页珍藏版）》请在麦多课文档分享上搜索。

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Convert to military drawing format. Add vendor CAGE 01295 for device type 01. Change VCCor GND current from 75 mA to 70 mA. Delete delta ICCcondition. Change VREF= 50 % to read VREF= 1.3 V. Editorial changes throughout. 87-02-11 Michael A. Frye B

2、 Change CAGE code to 67268. Remove vendor CAGE 04713 from drawing. Editorial changes in table I. Inactivate device type 01 for new design. Editorial changes throughout. 89-04-12 Michael A. Frye C Update boilerplate to MIL-PRF-38535 requirements. - jak 01-12-05 Thomas M. Hess D Update boilerplate. Ad

3、d device class V criteria. - jak 02-12-24 Thomas M. Hess E Add case outline S. Add table III, delta limits. Editorial changes throughout. jak 03-09-11 Thomas M. Hess F Add JEDEC Standard 7-A in paragraphs 2.2 and 4.4.1d. Update boilerplate paragraphs to the current MIL-PRF-38535 requirements. - LTG

4、09-11-23 Thomas M. Hess CURRENT CAGE CODE IS 67268 REV SHET REV SHET REV STATUS REV F F F F F F F F F F F F F OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 PMIC N/A PREPARED BY David W. Queenan DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil STANDARD MICROCIRCUIT DRAW

5、ING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE CHECKED BY D. A. DiCenzo APPROVED BY Nelson A. Hauck MICROCIRCUIT, DIGITAL, HIGH-SPEED CMOS, OCTAL D-TYPE FLIP-FLOP WITH THREE-STATE OUTPUTS, TTL COMPATIBLE INPUTS, MONOLITHIC SILICON DRAWING APPROVAL

6、DATE 86-03-21 AMSC N/A REVISION LEVEL F SIZE A CAGE CODE 14933 85507 SHEET 1 OF 13 DSCC FORM 2233 APR 97 5962-E044-10 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 85507 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS,

7、OHIO 43218-3990 REVISION LEVEL F SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and a

8、re reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the following examples. For device classes M and Q: 85507 01 R A Drawing number Device type (see 1.2.2) Case outline(se

9、e 1.2.4) Lead finish(see 1.2.5)For device class V: 5962 - 85507 01 V R A Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2)Device class designatorCase outline (see 1.2.4) Leadfinish (see 1.2.5) / (see 1.2.3) /Drawing number 1.2.1 RHA designator. Device classes Q and V

10、RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.

11、2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 54HCT374 Octal D-type flip-flop with three-state outputs, TTL compatible inputs 1.2.3 Device class designator. The device class designator is a single letter identifying the

12、product assurance level as listed below. Since the device class designator has been added after the original issuance of this drawing, device classes M and Q designators will not be included in the PIN and will not be marked on the device. Device class Device requirements documentation M Vendor self

13、-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STA

14、NDARD MICROCIRCUIT DRAWING SIZE A 85507 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 3 DSCC FORM 2234 APR 97 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style R

15、 GDIP1-T20 or CDIP2-T20 20 Dual-in-line S GDFP2-F20 or CDFP3-F20 20 Flat pack 2 CQCC1-N20 20 Square leadless chip carrier 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. 1.3 Absolute maximum ratings. 1/ 2

16、/ Supply voltage range (VCC) -0.5 V dc to +7.0 V dc DC input voltage . -0.5 V dc to VCC+0.5 V dc DC output voltage . -0.5 V dc to VCC+0.5 V dc Clamp diode current. 20 mA DC output current (per pin) 35 mA DC VCCor GND current (per pin) . 70 mA Storage temperature range (TSTG) . -65C to +150C Maximum

17、power dissipation (PD) 500 mW 3/ Lead temperature (soldering, 10 seconds) +260C Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 Junction temperature (TJ) +175C 1.4 Recommended operating conditions. Supply voltage range (VCC) +4.5 V dc to +5.5 V dc Case operating temperature range (TC) .

18、 -55C to +125C Input rise or fall time (VCC= 4.5 V) 0 to 500 ns Minimum setup time, data to clock (ts): VCC= 4.5 V: TC= +25C . 20 ns C= -55C to +125C . 30 ns Minimum clock pulse width (tw): VCC= 4.5 V: TC= +25C . 20 ns C= -55C to +125C . 30 ns Minimum hold time, clock to data (th): VCC= 4.5 V: TC= +

19、25C . 10 ns C= -55C to +125C . 15 ns Maximum clock frequency (fmax): VCC= 4.5 V: TC= +25C . 25 MHz C= -55C to +125C . 17 MHz 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability

20、. 2/ Unless otherwise specified, all voltages are referenced to ground. 3/ For TC= +100C to +125C, derate linearly at 12 mW/C. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 85507 DEFENSE SUPPLY CENTER COLUMBUS C

21、OLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 4 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the is

22、sues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Stand

23、ard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Documen

24、t Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents cited in the solicitation or contract. ELECTR

25、ONIC INDUSTRIES ALLIANCE (EIA) JEDEC Standard No. 7-A - Standard for Description of 54/74HCXXXXX and 54/74HCTXXXXX High-Speed CMOS Devices. (Copies of these documents are available online at http:/www.jedec.org or from Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834).

26、 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMEN

27、TS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function

28、 as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as

29、specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3

30、Truth table. The truth table shall be as specified on figure 2. 3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3. 3.2.5 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 4. Provided by IHSNot for ResaleNo reproducti

31、on or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 85507 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 5 DSCC FORM 2234 APR 97 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise

32、 specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table

33、II. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the man

34、ufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix

35、 A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V,

36、a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in

37、 MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, th

38、e requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing.

39、3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. 3.9 Verification and review for device class M. For device class M, DSCC,

40、DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices co

41、vered by this drawing shall be in microcircuit group number 38 (see MIL-PRF-38535, appendix A). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 85507 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISI

42、ON LEVEL F SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Test conditions -55C TC +125C 1/ unless otherwise specified Group A subgroups Limits Unit Min Max High-level output voltage VOHVIN= VIHor VIL, VIH= 2.0 V IOH= -20 A, VIL= 0.8 V VCC= 4.5 V 1, 2, 3 4.

43、4 V VIN= VIHor VIL, VIH= 2.0 V IOH= -6.0 mA, VIL= 0.8 V VCC= 4.5 V 1, 2, 3 3.7 Low-level output voltage VOLVIN= VIHor VIL, VIH= 2.0 V IOL= +20 A, VIL= 0.8 V VCC= 4.5 V 1, 2, 3 0.1 V VIN= VIHor VIL, VIH= 2.0 V IOL= +6.0 mA, VIL= 0.8 V VCC= 4.5 V 1, 2, 3 0.4 High-level input voltage VIH2/ VCC= 4.5 V 1

44、, 2, 3 2.0 V Low-level input voltage VIL2/ CC= 4.5 V 1, 2, 3 0.8 V Quiescent current ICCVIN= VCCor GND, VCC= 5.5 V 1, 2, 3 160 A Input leakage current IINVIN= VCCor GND, VCC= 5.5 V 1, 2, 3 1.0 A Three-state output leakage current IOZVIN(Enable) = VIH, All other inputs VIN= VIHor VILVOUT= VCCor GND 1

45、, 2, 3 10.0 A Input capacitance CINVIN= 0.0 V, TC= +25C See 4.4.1d 4 10 pF Functional tests See 4.4.1b 7 Additional quiescent supply current ICCVIN = 2.4 V or 0.5 V, any one input VIN= VCCor GND, other inputs VCC= 5.5 V IOUT= 0.0 A 1, 2, 3 3.0 mA Propagation delay time, CLK to mQ tPLH, tPHL3/ CL= 50

46、 pF See figure 4 9 36 ns 10, 11 54 Propagation delay time, output enable, OE to mQ tPZH, tPZL3/ CL= 50 pF See figure 4 9 35 ns 10, 11 53 Propagation delay time, output disable, OE to mQ tPHZ, tPLZ3/ CL= 50 pF See figure 4 9 35 ns 10, 11 53 Transition time, high-to-low low-to-high tTHL, tTLH4/ CL= 50

47、 pF See figure 4 9 12 ns 10, 11 18 See footnotes on next sheet. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 85507 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 7 DSCC FORM 223

48、4 APR 97 TABLE I. Electrical performance characteristics Continued. 1/ For a power supply of 5.0 V 10%, the worst case output voltages (VOHand VOL) occur for HCT at 4.5 V. Thus, the 4.5 V values should be used when designing with this supply. The worst case leakage currents (IINand ICC) occur for CMOS at the higher voltage and so the 5.5 V values should be used. Power dissipation capacitance (CPD), typically 40 pF, determines the no load dynamic power consumption, PD= CPD VCC2f+ICC VCC; and the no load dynamic current consumption, IS= CPDVCCf+ICC. 2/ Test not requi