DLA SMD-5962-84052 REV D-1990 MICROCIRCUITS DIGITAL CMOS 16 BIT MICROPROCESSOR MONOLITHIC SILICON《硅单片 16比特微处理器 氧化物半导体数字微型电路》.pdf

《DLA SMD-5962-84052 REV D-1990 MICROCIRCUITS DIGITAL CMOS 16 BIT MICROPROCESSOR MONOLITHIC SILICON《硅单片 16比特微处理器 氧化物半导体数字微型电路》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-84052 REV D-1990 MICROCIRCUITS DIGITAL CMOS 16 BIT MICROPROCESSOR MONOLITHIC SILICON《硅单片 16比特微处理器 氧化物半导体数字微型电路》.pdf（28页珍藏版）》请在麦多课文档分享上搜索。

1、. REV SHEET REV SHEET W b O322363 OTL W Dl c c cc c 23 24 25 26 27 28 - LTR - B C - 0 REV STATUS REV DC OF SHEETS SHEET 12 I REVISIONS cc CD cc cc c cc c cc cc c c 3 45 67 8- 10 11 12 13 14 15 16 17 15 19 20 21 DESCRIPTION :hange case 2 to case X. Changes to recommended operating conditions, table I

2、, and table II. Convert to military drawing format. Editorial changes throughout. Add vendor CAGE 34649. 4dd device type 02. Change drawing CAGE code. Editorial changes throughout. CLK rise time (tCHlCH2) device type O1 and 02 changed from 15 ns maximum to 10 ns maximum. type O1 and O2 changed from

3、15 ns maximum to 10 ns maximum. Table I: RD inactive to next address active (tRHAv) device type 02 changed from -45 ns minimum to -40 ns minimum. Editorial changes throughout. CLK fall time (tCL2CLl) device IATE (YR-MO-DA) APPROVED I 1- 37 FEB 26 59 OCT 25 CURRENT CAGE CODE 67268 PMIC NA STANDARDIZE

4、D M I LITA RY I PREPAREDBY DRAWING PPROVED BY J THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS IlATE REVISION LEVEL AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC NIA DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 MICROCIRCUITS, DIGITAL, CMOS, 16 BIT MICROPROCESSOR, MONOLITHIC SILICON SH

5、EET 1 OF 25 IESC FORM 193-1 SEP 87 *US. GOVERNMfNT PRINTING OFFICI: 1987 - 748-11916(w12 5962-El 688 DISTRIRUTION STATEMENT A. Approved lor publlc release; dislrlbulloci Is unliinited. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-b 0322364 T38 STA

6、NDARDIZED MILITARY DRAWING _ 1. SCOPE 1.1 SCO e. This drawing describes device requirements for class B microcircuits in accordance iith 1. Ottl( E: IVR! . 748-I?l.h(PLI DESC FORM 193A SEP a7 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-m 9999996

7、0322379 Yb9 m STANDARDIZED SIZE A f u) I 0 +-r 84052 4 o J I DEFENSE ELECTRONICS SUPPLY CENTER DAMON, OHIO 45444 I I I I I I I I I I SHEET REVISION LEVEL C 17 O I- H - LI r - - W I- O z W W v) I u z u .- d * Y o O J r J o VI -* lu% Cd mu V* X mal c O TC o4 L XK u0 c .I- -I- si2 4s cn LO OU %aJ L v)

8、*e, ce, e,* EC am LL .Y 4 353 Um e, LO c cz *- wc wo 3% W t- O DESC FORM 193A SEP a7 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-D 9999996 0122380 180 STANDARDIZED SIZE A Maximum mode 84052 t MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAY

9、TON, OHIO 45444 NOTES : 1. 2. 3. 4. All signals switch between Vo and VOL uh,ess otherw,;e specified. RDY is sampled near the end o! T2, Ti, and TW to determine if TN machines states are to be inserted. Cascade address is valid between first and second INTA cycles. Two INTA cycles run back-to-back.

10、floating during both INTA cycles. second INTA cycle. Signals are shown for reference only. The issuance of the bus controlled command and control signals (m, m, m, ToR(T, m, m, m, and m) as the active high bus controller CENS All timing measurements are made at 1.5 V unless otherwise noted. Status i

11、nactive in state just prior to T4. . The 80C86 local addr-data bus is Control signals are shown for the 5. 6. 7. 8. REVISION LEVEL SHEET C 18 FIGURE 3. AC test circuit and waveforms - Continued. OESC FORM 193A SEP a7 Provided by IHSNot for ResaleNo reproduction or networking permitted without licens

12、e from IHS-,-,-W 9999996 0122381 017 = STANDARDIZED MILITARY DRAW IN G DEFENSE ELECTRONICS SUPPLY CENTER - DAYTON, OHIO 45444 - 3 Z o SIZE A 84052 REVISION LEVEL SHEET C 19 w O O z W O z c 5; W 3 o W IT I-N aJaJ SL I- W I- O a U aJ =I S c s O u .C I I I DESC FORM 193A SEP 87 Provided by IHSNot for R

13、esaleNo reproduction or networking permitted without license from IHS-,-,-m b 0322382 T53 m AC test circuit OUTPUT FROM TEST POINT DEVICE UNDER 7 TEST _L CL (SEE NOTE) T NOTE: CL = 100 pF stray and jig capacitance RESET TIMING -4 250p + CLK RESET 2 4 CLK CYCLES AC testing input, output waveform. INP

14、UT VIH to.4 v 1.5 V 1.5 v VIL -0.4 V OUTPUT “OH AC testing: All input signals (other than CLK) must switch between VIL(maxi -0.4 v and vIH(min) +0.4 v. ZLK mus switch between 0.4 V and V:c -0.4 V. tr and tf _ are driven at 1 nsIV. FIGURE 3. AC test circuit and waveforms - Continued. STANDARDIZED MIL

15、ITARY DRAWING I A I I 84052 DEFENSE ELECTRONICS SUPPLY CENTER REVISION LEVEL SHEET DAYTON, OHIO 45444 C 20 DESC FORM 193A SEP 87 xi U S GOVERNMENT PRINTING OFFICE 1988-550-547 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-m b 0322383 T m STANDARDIZ

16、ED MILITARY DRAWING 3.5 Marking. Marking shall be in accordance with MIL-STD-883 (see 3.1 herein). The part shall be marked with the part number listed in 1.2 herein. may also be marked as listed in MIL-BUL-103 (see 6.6 herein). in order to be listed as an approved source of supply in MIL-BUL-103 (s

17、ee 6.6 herein). certificate of compliance submitted to DESC-ECC prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-STD-883 (see 3.1 herein) and the requirements herein. herein) shall be provided with each lot of microcircuits de

18、livered to this drawing. with MIL-S1D-883 -T-9- see 3.1 herein). In addition, the manufacturers part number 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer The 3.7 Certificate of conformance. A certificate of conformance as required in MIL-STD-883 (se

19、e 3.1 3.8 Notification of chan e. Notification of change to DESC-ECC shall be required in accordance SIZE A 840 5 2 A 3.9 Verification and review. DESC, DESCs agent, and the acquiring activity retain the option ta review the manufacturers facility and applicable required documentation. shall be made

20、 available on shore at the option of the reviewer. Offshore documentation 4. QUALITY ASSURANCE PROVISIONS DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with 4.2 Screening. Screening shall be in accordance w

21、ith method 5004 of MIL-STD-883, and shall be section 4 of MIL-M-38510 to the extent specified in MIL-STD-883 (see 3.1 herein). conducted on al 1 devices prior to quality conformance inspection. shall apply: The following additional criteria a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condi

22、tion A, B, C, or D using the circuit submitted with the certificate of compliance (see 3.6 herein). REVISION LEVEL SHEET C 21 (2) TA = +125C, minimum. except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. b. Interim and final electrical test p

23、arameters shall be as specified in table II herein, 4.3 Quality conformance inspection. Quality conformance inspection shall be in accordance with method 5005 of MIL-STD-883 including groups A, By C, and D inspections. cri teria shall apply. The following additional 4.3.1 Group A inspection. a. Test

24、s shall be as specified in table II herein. b. c. Subgroups 5 and 6 in table I, method 5005 of MIL-STD-883 shall be omitted. Subgroup 4 (CIN, COUT, and CI 0 measurements) shall be measured.only for the initial test and after process or design changes which may affect capacltance. size of 5 devices w

25、ith zero rejects shall be required. Subgroups 7 and 8 shall consist of verifying the functionality of the device. form a part of the vendors test tape and shall be maintained and available from approved source of supply. A minimum sample d. These tests Provided by IHSNot for ResaleNo reproduction or

26、 networking permitted without license from IHS-,-,-m 9999996 0322384 826 M i STANDARDIZED SIZE A TABLE II. Electrical test requirements. 84052 I I I I MIL-STO-883 test requirements I Subgroups (per method I I I 5005, table I) I I I MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 4544

27、4 /Initial electrical parameters (method 5004) I I I REVISION LEVEL SHEET n 22 IFinal electrical test parameters (method 5004) I 1*,2,3,7,8,9,10,11 I I 1 I IGroup A test requirements (method 5005) I 1,2,3,4,7,8,9,10,11 I 1 I IGroups C and D end-point electrical parameters I l I (method 5005) I 2,8 (

28、125OC) ,10 I * PDA applies to subgroup 1. 4.3.2 Groups C and D inspections. a. b. End-point electrical parameters shall be as specified in table II herein. Steady-state life test, method 1005 of MIL-STD-883 conditions. (1) (2) TA = +125C, minimum. (3) Test duration: Test condition A, E, C, or O usin

29、g the circuit submitted with the certificate of compliance (see 3.6 herein). 1,000 hours, except as permitted by method 1005 of MIL-STD-883. 5. PACKAGING 5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL -M-32510. 6. NOTES 6.1 Intended use. Microcircuits conf

30、orming to this drawing are intended for use when military specifications do not exist and qualified military devices that will perform the required function are not available for OEM application. When a military specification exists and the product covered by this drawing has been qualified for list

31、ing on QPL-38510, the device specified herein will be inactivated and will not be used for new design. for all applications. covered by a contractor-prepared specification or drawing. with the users of record tor the indTvidua1 documents. This coordination will be accomplished in accordance with MIL

32、-STD-481 using DD Form 1693, Engineering Change Proposal (Short Form). 6.4 Record of users. Military and industrial users shall inform Defense Electronics Supply Center when a system application requires configuration control and the applicable SMD. DESC will maintain a record of users and this list

33、 will be used for coordination and distribution of changes to the drawings. DESC-ECC, telephone (513) 296-6022. The QPL-38510 product shall be the preferred item 6.2 Replaceability. Microcircuits covered by this drawing will replace the same generic device 0.3 Configuration control of SMDs. All prop

34、osed changes to existing SMDs will be coordinated Users of drawings covering microelectronics devices (FSC 5962) should contact 6.5 Comments. Comments on this drawing shpuld be directed to DESC-ECC, Dayton, Ohio 45444, or telephone (513) 296-8525. ,ESC FORM 193A SEP a7 Q U. S. GOVERNMENT PRINTING OF

35、FICE 1989-749.033 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-m b 0322385 b2 m . STANDARDIZED M I LITA RY DRAW IN G DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 6.6 Symbols, definitions, and functional descriptions. The symbols, definitio

36、ns, and functional lescription for this device shall be as follows: SIZE A 84052 REVISION LEVEL SHEET C 23 Name and function (Minimum and maximum mode) ADDRESS DATA BUS: lower byte of the data bus, pins D7-Do. to be transferred on the lower portion of the bus in memory or 1/0 operations. Eight-bit o

37、riented devices tied to the lower half would normally use A to condition chip select functions (see m). held at high impedance to the last valid logic level during interrupt acknowledge and 1 oca1 bus II hol d acknowledge“ or “grant sequence .I1 These lines constitute the time multi lexed memory/IO

38、address (TI) and data (T2, T3, TW, T4) bus. Ao is analogous to %E B for the It is LOW during T1 when a byte is These lines are active HIG a and are ADDRESSSTATUS: lines for memory operations. During 1/0 operations these lines are LOW. During memory and 1/0 operations, status information is available

39、 on these lines during T2, T3, Tw, and T4. s6 is always low. interrupt enable FLAG bit (S5) is updated at the beginning of each CLK cycle. During Ti, these are the four most significant address The status of the S4 and S3 are encoded as follows: I I I I I Characteristics I I I I s4 I I s3 I i 1 I I

40、I o (LOW) I I O I I 1 (HIGH) I I 1 .I IS6 is 0 (LOW) I I I 0. I Alternate data I 1 I .Stack I O 1 Code or none I 1 I Data I This information indicates which segment register is presently being used for data accessing. impedance to the last valid logic level during local bus “hold acknowledge“ or “gr

41、ant sequence“. These lines are held at high BUS HIGH ENABLE/STATUS: During Ti the bus high enable signal (BREI should be used to qnable data onto the most significant half of the data bus, pins lI15-D. Eight bit oriented devices tied to the upper half of the bus would normally use DHE to condition c

42、hip select functions. read, write, and interrupt. acknowledge cycles when a byte is to be transferred on the high portion of the bus. The S7 status information is available during T2, T3, and T4. The signal is active LOW, and is held to high impedance to the last valid logic level during interrupt a

43、cknowledge and local bus “hold acknowledge“. It is LOW during Ti for the first interrupt acknowledge cycle. BHE is LOW during TI for DESC FORM 193A SEP a7 *U. S. GOVERNMENT PRINTING OFFICE: 19riR-519-90d Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-

44、,-9999996 0322386 bT9 Name and function (Minimum and maximum mode) STANDARDIZED MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 SYMBOL m 1 EAD Y IIJTR TEST ilII TESET SIZE A 84052 REVISION LEVEL SHEET C 24 I I I I i mE: I Ao I Characteristics I I I l I I1 I IO I O I Whole word

45、I IO I 1 I Upper byte from/ I I I I to odd address I Il I O I Lower byte from/ I I I I to even address I I1 I 1 I None I READ: erforming a memory or 1/0 read cycle, depending on the state of the 5 or M rt; I pin. This signal is used to read devices which reside on the microprocessor local bus. LOW d

46、uring T2, T3, and TW of any read cycle, and remains HIGH in T2 until the microprocessor local bus has floated. logic one state during “hold acknowledge“ or “grant sequence.“ Read strobe indicates that the processor is RD is active This line is held at a high impedance READY: complete the data transf

47、er. The ROY signal from memory or 1/0 is synchronized by the Clock Generator to form READY. This signal is active HIGH. The microprocessor READY input is not synchronized. Correct operation is not guaranteed if the setup and hold times are not met. Is the acknowledgement from the addressed memory or

48、 1/0 device that will INTERRUPT REQUEST: cycle of each instruction to determine if the processor should enter into an interrupt acknowledge operation. vector lookup table located in system memory. software resetting the interrupt enable bit. This signal is active HIGH. A level triggered input which

49、is sampled during the last clock A subroutine is vectored to via an interrupt It can be internally masked by INTR is internally synchronized. m: Input is examined by the “Wait“ instruction. If the input is LOW execution continues, otherwise the processor waits in an “Idle“ state. is synchronized internally during each clock cycle on the le