DLA SMD-5962-84044 REV G-2011 MICROCIRCUIT DIGITAL HIGH-SPEED CMOS DUAL 4-INPUT NOR GATE MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED C Convert to military drawing format. Add vendor CAGE 18714 for device type 01. Editorial changes throughout. 86-11-21 N. A. Hauck D Add vendor CAGE 27014 to case 2. Inactivate case 2 for new design. Inactivate case A for new design. Add vendor CAG

2、E 27014 to case D. Inactivate case C for new design. 87-12-05 M. A. Frye E Update boilerplate to MIL-PRF-38535 requirements. - CFS 01-08-28 Thomas M. HessF Made change to paragraph 3.5. Update boilerplate to MIL-PRF-38535 requirements. LTG 05-03-17 Thomas M. Hess G Update boilerplate paragraphs to t

3、he current MIL-PRF-38535 requirements. - LTG 11-07-26 Thomas M. Hess Current CAGE CODE is 67268 REV SHET REV SHET REV STATUS REV G G G G G G G G G G OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 PMIC N/A PREPARED BY Greg A. Pitz DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mi

4、l STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A CHECKED BY D. A. DiCenzo APPROVED BY N. A. Hauck MICROCIRCUIT, DIGITAL, HIGH-SPEED CMOS, DUAL 4-INPUT NOR GATE, MONOLITHIC SILICON DRAWING APPROVAL DATE 84-06-08 RE

5、VISION LEVEL G SIZE A CAGE CODE 14933 84044 SHEET 1 OF 10 DSCC FORM 2233 APR 97 5962-E451-11 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84044 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL G S

6、HEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 84044

7、01 C A Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 54HC4002 Dual 4-input NOR gate 1.2.2 Case outline(s). The case outline(s) are

8、as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style A GDFP5-F14 or CDFP6-F14 14 Flat pack B GDFP4-F14 14 Flat packC GDIP1-T14 or CDIP2-T14 14 Dual-in-lineD GDFP1-F14 or CDFP2-F14 14 Flat pack 2 CQCC1-N20 20 Square leadless chip carrier 1.2.3 Le

9、ad finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. 1/ 2/ 3/ Supply voltage range (VCC) -0.5 V dc to +7.0 V dc DC input voltage range (VIN) -0.5 V dc to VCC+ 0.5 V dc DC output voltage range (VOUT) . -0.5 V dc to VCC+ 0.5 V dc Clamp diode current. 2

10、0 mA DC output current (per pin) 25 mA DC VCCor GND current (per pin) . 50 mA Storage temperature range (TSTG) . -65C to +150C Maximum power dissipation (PD) . 500 mW 4/ Lead temperature (soldering, 10 seconds) +260C Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 Junction temperature (

11、TJ) +175C 5/ 1.4 Recommended operating conditions. 2/ 3/ Supply voltage range (VDD) +2.0 V dc to +6.0 V dc Case operating temperature range (TC) . -55C to +125C Input rise or fall time: VCC= 2.0 V . 0 to 1000 ns VCC= 4.5 V . 0 to 500 ns VCC= 6.0 V . 0 to 400 ns _ 1/ Stresses above the absolute maxim

12、um rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Unless otherwise specified, all voltages are referenced to ground. 3/ The limits for the parameters specified herein shall apply over the full specified VCC

13、range and case temperature range of -55C to +125C. 4/ For TC= +100C to +125C, derate linearly at 12 mW/C. 5/ Maximum junction temperature shall not be exceeded except for allowable short duration burn-in screening conditions in accordance with method 5004 of MIL-STD-883. Provided by IHSNot for Resal

14、eNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84044 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL G SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The followin

15、g specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, Gen

16、eral Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit

17、Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following document(s) form a part of this document

18、 to the extent specified herein. Unless otherwise specified, the issues of these documents cited in the solicitation or contract. JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEDEC Standard No. 7 - Standard for Description of 54/74HCXXXXX and 54/74HCTXXXXX Advanced High-Speed CMOS Devices. (Copi

19、es of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10thStreet, Suite 240-S Arlington, VA 22201). 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text

20、of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN cla

21、ss level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance w

22、ith the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device.

23、 These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall b

24、e as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. Provi

25、ded by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84044 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL G SHEET 4 DSCC FORM 2234 APR 97 3.2.4 Logic diagram. The logic diagram shall be as specified on figur

26、e 3. 3.2.5 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 4. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the

27、full (case or ambient) operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, append

28、ix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked as listed in MIL-HDBK-103 (see 6.6 herein). 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38

29、535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed

30、 as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DLA Land and Maritime -VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirement

31、s herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DLA Land and Maritime -VA shall be required for any change

32、 that affects this drawing. 3.9 Verification and review. DLA Land and Maritime, DLA Land and Maritimes agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option

33、of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84044 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL G SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics

34、. Test Symbol Test conditions -55C TC+125C unless otherwise specified 1/ Group A subgroups Limits Unit Min Max High level output voltage VOHVIN= VIHor VILIOH= 20 A VCC= 2.0 V 1, 2, 3 1.9 V VCC= 4.5 V 4.4 VCC= 6.0 V 5.9 VIN= VIHor VILIOH= -4.0 mA VCC= 4.5 V 3.7 VIN= VIHor VILIOH= -5.2 mA VCC= 6.0 V 5

35、.2 Low level output voltage VOLVIN= VIHor VILIOL= +20 A VCC= 2.0 V 1, 2, 3 0.1 V VCC= 4.5 V 0.1 VCC= 6.0 V 0.1 VIN= VIHor VILIOL= +4.0 mA VCC= 4.5 V 0.4 VIN= VIHor VILIOL= +5.2 mA VCC= 6.0 V 0.4 High level input voltage VIH2/ VCC= 2.0 V 1, 2, 3 1.5 V VCC= 4.5 V 3.15 VCC= 6.0 V 4.2 Low level input vo

36、ltage VIL2/ VCC= 2.0 V 1, 2, 3 0.3 V VCC= 4.5 V 0.9 VCC= 6.0 V 1.2 Input capacitance CINVIN= 0.0 V, TC= +25C See 4.3.1c 4 10 pF Quiescent supply current ICCVCC= 6.0 V VIN= VCCor GND 1, 2, 3 40 A Input leakage current IINVCC= 6.0 V VIN= VCCor GND 1, 2, 3 1.0 A Functional tests See 4.3.1d 7 See footno

37、tes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84044 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL G SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteris

38、tics - Continued. Test Symbol Test conditions -55C TC+125C unless otherwise specified 1/ Group A subgroups Limits Unit Min Max Propagation delay time, input to output, high-to-low, low-to-high tPHL, tPLH3/ TC= +25C CL= 50 pF 10% See figure 4 VCC= 2.0 V 9 120 ns VCC= 4.5 V 24 VCC= 6.0 V 20 TC= -55C a

39、nd +125C CL= 50 pF 10% See figure 4 VCC= 2.0 V 10, 11 180 ns VCC= 4.5 V 36 VCC= 6.0 V 31 Transition time high-to-low, low-to-high tTHL, tTLH4/ TC= +25C CL= 50 pF 10% See figure 4 VCC= 2.0 V 9 75 ns VCC= 4.5 V 15 VCC= 6.0 V 13 TC= -55C and +125C CL= 50 pF 10% See figure 4 VCC= 2.0 V 10, 11 110 ns VCC

40、= 4.5 V 22 VCC= 6.0 V 19 1/ For a power supply of 5 V 10% the worst case output voltages (VOHand VOL) occur for HC at 4.5 V. Thus, the 4.5 V values should be used when designing with this supply. Worst case VIHand VILoccur at VCC= 5.5 V and 4.5 V respectively. (The VIHvalue at 5.5 V is 3.85 V.) The

41、worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage, and so the 6.0 V values should be used. Power dissipation capacitance (CPD), typically 20 pF, determines the no load dynamic power consumption, PD= CPDVCC2+ ICCVCC, and the no load dynamic current consumption, IS= C

42、PDVCCf + ICC. 2/ VIHand VILtests are not required if they are applied as forcing functions for the VOHand VOLtests. 3/ Propagation delay times, when VCC= 2.0 V and 6.0 V shall be guaranteed, if not tested, to the specified parameters. 4/ Transition time (tTHL, tTLH), if not tested, shall be guarante

43、ed to the specified parameters. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84044 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL G SHEET 7 DSCC FORM 2234 APR 97 Device type 01 Case outlines A,

44、B, C, and D 2 Terminal number Terminal symbol 1 1Y NC2 1A 1Y 3 1B 1A 4 1C 1B 5 1D NC 6 NC 1C7 GND NC 8 NC 1D9 2A NC 10 2B GND 11 2C NC 12 2D NC13 2Y 2A 14 VCC2B 15 NC 16 2C17 NC 18 2D19 2Y 20 VCCNC = No internal connection FIGURE 1. Terminal connections. (Each gate) Input Output Y A B C D L L L L H

45、H X X X L X H X X L X X H X L X X X H L H = High voltage level L = Low voltage level X = Irrelevant FIGURE 2. Truth table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84044 DLA LAND AND MARITIME COLUMBUS, OHIO

46、 43218-3990 REVISION LEVEL G SHEET 8 DSCC FORM 2234 APR 97 FIGURE 3. Logic diagram. NOTES: 1. CL= 50 pF minimum or equivalent (includes test jig and probe capacitance). 2. Input signal from pulse generator: VIN= 0.0 V to VCC; PRR 1MHz; ZO= 50; tr = 6.0 ns; tf= 6.0 ns; trand tfshall be measured from

47、0.1 VCCto 0.9 VCC and from 0.9 VCC to 0.1 VCC, respectively; duty cycle = 50 percent. 3. Timing parameters shall be tested at a minimum input frequency of 1 MHz. 4. The outputs are measured one at a time with one transition per measurement. FIGURE 4. Switching waveforms and test circuit. Provided by

48、 IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84044 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL G SHEET 9 DSCC FORM 2234 APR 97 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection.