DLA SMD-5962-84011 REV G-2005 MICROCIRCUIT DIGITAL BIPOLAR ADVANCED LOW-POWER SCHOTTKY TTL DUAL D-TYPE POSITIVE EDGE TRIGGERED FLIP-FLOPS WITH CLEAR AND RESET MONOLITHIC SILICON《硅单.pdf

《DLA SMD-5962-84011 REV G-2005 MICROCIRCUIT DIGITAL BIPOLAR ADVANCED LOW-POWER SCHOTTKY TTL DUAL D-TYPE POSITIVE EDGE TRIGGERED FLIP-FLOPS WITH CLEAR AND RESET MONOLITHIC SILICON《硅单.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-84011 REV G-2005 MICROCIRCUIT DIGITAL BIPOLAR ADVANCED LOW-POWER SCHOTTKY TTL DUAL D-TYPE POSITIVE EDGE TRIGGERED FLIP-FLOPS WITH CLEAR AND RESET MONOLITHIC SILICON《硅单.pdf（12页珍藏版）》请在麦多课文档分享上搜索。

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED C Change power dissipation to 22 mW. Change clock pulse setup, hold, and propagation delay times. Change clock frequency. Change to military drawing format. Change code ident. no. to 67268. Change table I footnotes. Add figure 4. Editorial changes

2、throughout. 88-04-06 M. A. Frye D Changes in accordance with NOR 5962-R246-92. -tmh 92-07-10 Monica L. Poelking E Changes in accordance with NOR 5962-R097-93. -ltg 93-03-12 Monica L. Poelking F Update to reflect latest changes in format and requirements. Editorial changes throughout. -les 02-07-29 R

3、aymond Monnin G Update to reflect latest changes in format and requirements. Correct paragraph in 3.5. Editorial changes throughout. les 05-07-26 Raymond Monnin THE ORIGINAL FIRST PAGE OF THIS DRAWING HAS BEEN REPLACED. CURRENT CAGE CODE 67268 REV SHET REV SHET REV STATUS REV G G G G G G G G G G G O

4、F SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 PMIC N/A PREPARED BY Joseph A. Kirby DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Raymond Monnin COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael A. Frye MICROCI

5、RCUIT, DIGITAL, BIPOLAR, ADVANCED LOW-POWER SCHOTTKY TTL, DUAL D-TYPE AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 84-05-04 POSITIVE EDGE TRIGGERED FLIP-FLOPS WITH CLEAR AND RESET, MONOLITHIC SILICON AMSC N/A REVISION LEVEL G SIZE A CAGE CODE 14933 84011 SHEET 1 OF 11 DSCC FORM 22

6、33 APR 97 5962-E396-05 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84011 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL G SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing

7、 describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 84011 01 C X Drawing number Device type (see 1.2.1) Case outline(se

8、e 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type. The device type identify the circuit function as follows: Device type Generic number Circuit function 01 54ALS74 Dual D-type positive-edge-triggered flip-flops 1.2.2 Case outlines. The case outlines are as designated in MIL-STD-1835 and as follows: O

9、utline letter Descriptive designator Terminals Package style C GDIP1-T14 or CDIP2-T14 14 dual-in-line D GDFP1-F14 or CDFP2-F14 14 flat 2 CQCC1-N20 20 square chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Supply voltage . -0

10、.5 V dc to +7.0 V dc Input voltage range -1.5V dc at -18 mA to +7.0 V dc Storage temperature range -65C to +150C Maximum power dissipation (PD) 1/ 22 mW Lead temperature (soldering, 10 seconds) . +300C Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 Junction temperature (TJ) +175C 1.4 R

11、ecommended operating conditions. Supply voltage range (VCC) . +4.5 V dc minimum to +5.5 V dc maximum Minimum high level input voltage (VIH) . 2.0 V dc Maximum low level input voltage (VIL) : TC= +125C . 0.7 V dc TC= +25C . 0.8 V dc TC= -55C 0.8 V dc Setup time before CLK, data (tsu) . 15 ns Setup ti

12、me before CLK, PRE or CLR inactive (tsu) 10 ns _ 1/ Maximum power dissipation is defined as VCCx ICC, and must withstand the added PDdue to short-circuit test; e.g., IO. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SI

13、ZE A 84011 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL G SHEET 3 DSCC FORM 2234 APR 97 Hold time, data after CLK (th) . 0 ns Pulse duration, PRE or CLR low (tW) . 15 ns Pulse duration, CLK high or low (tW) 16.5 ns Clock frequency (fCLOCK) . 30 MHz Case operating temperatu

14、re range (TC) -55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in t

15、he solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPA

16、RTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 70

17、0 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations

18、unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufa

19、cturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. T

20、his QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordan

21、ce with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accor

22、dance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth tables. The truth tables shall be as specified on figure 2. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIR

23、CUIT DRAWING SIZE A 84011 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL G SHEET 4 DSCC FORM 2234 APR 97 3.2.4 Logic diagrams. The logic diagrams shall be as specified on figure 3. 3.2.5 Test circuits and switching waveforms. The test circuits and switching waveforms shall b

24、e as specified on figure 4. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requ

25、irements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also

26、be marked. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when

27、the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved sou

28、rce of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered

29、to this drawing. 3.8 Notification of change. Notification of change to DSCC-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documen

30、tation. Offshore documentation shall be made available onshore at the option of the reviewer. 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL

31、-STD-883, and shall be conducted on all devices prior to quality conformance inspection. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition A or D. The test circuit shall be maintained by the manufacturer under document revision level contr

32、ol and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. (2) TA= +125C, minimum. b. Interim and final el

33、ectrical test parameters shall be as specified in table II herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DR

34、AWING SIZE A 84011 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL G SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions -55C TC +125C 1/ 2/ unless otherwise specified Group A subgroupsDevice type Limits Unit Min MaxHigh level

35、 output voltage VOHVCC= 4.5 V, VIH= 2.0 V, VIL= 0.7 V 2 All 2.5 V IOH= -0.4 mA 3/ VIL= 0.8 V 1, 3 2.5 Low level output voltage VOL VCC= 4.5 V, VIH= 2.0 V, VIL= 0.7 V 2 All 0.4 V IOL= 4.0 mA 3/ VIL= 0.8 V 1, 3 0.4 Input clamp voltage VIC VCC= 4.5 V IIN= -18 mA 1, 2, 3 All -1.5 V CLK or D -0.2 Low lev

36、el input current IIL VCC= 5.5 V, VIN= 0.4 V, All other inputs = 4.5 V PRE or CLR 1, 2, 3 All -0.4 mA CLK or D 20 High level input current IIH1 VCC= 5.5 V, VIN= 2.7 V, All other inputs = 0.0 V PRE or CLR 1, 2, 3 All 40 A CLK or D 0.1 IIH2 VCC= 5.5 V, VIN= 7.0 V, All other inputs = 0.0 V PRE or CLR 1,

37、 2, 3 All 0.2 mA Output current IOVCC= 5.5 V, VOUT= 2.25 V 4/ 1, 2, 3 All -20 -112 mA Supply current ICC VCC= 5.5 V, 5/ 1, 2, 3 All 4.0 mA Functional tests See 4.3.1c 6/ 7, 8 All Propagation delay time, tPLH1 VCC= 4.5 V to 5.5 V 9, 10, 11 All 3 18 ns PRE or CLR to Q or Q tPHL1 CL= 50 pF 9, 10, 11 Al

38、l 5 17 Propagation delay time, tPLH2 RL = 500 9, 10, 11 All 5 17 ns CLK to Q or Q tPHL2 See figure 4 7/ 9, 10, 11 All 5 18 1/ Unused inputs that do not directly control the pin under test must be 2.5 V or 0.4 V. 2/ Unused inputs shall not exceed 5.5 V or go less than 0.0 V. No input shall be floated

39、. 3/ All outputs must be tested. In the case where only one input at VILmaximum or VIHminimum produces the proper output state, the test must be performed with each input being selected as the VILmaximum or the VIHminimum input. Provided by IHSNot for ResaleNo reproduction or networking permitted wi

40、thout license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84011 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL G SHEET 6 DSCC FORM 2234 APR 97 4/ The output conditions have been chosen to produce a current that closely approximates one half of the true short circuit ou

41、tput current, IOS. Not more than one output will be tested at one time and the duration of the test condition shall not exceed 1 second. 5/ ICCis measured with D, CLK, and PRE grounded, then with D, CLK, and CLR grounded. 6/ Functional tests shall be conducted at input test conditions of GND VIL VOL

42、and VOH VIH VCC. 7/ Propagation delay limits are based on single output switching. Unused inputs = 3.5 V or 0.3 V. Device types 01 01 Case outlines C, D 2 Terminal number Terminal symbols 1 1 CLR NC 2 1D 1 CLR 3 1CLK 1D 4 1PRE 1CLK 5 1Q NC 6 1 Q 1PRE 7 GND NC 8 2 Q 1Q 9 2Q 1 Q 10 2PRE GND 11 2CLK NC

43、 12 2D 2 Q 13 2 CLR 2Q 14 VCC2PRE 15 - - - NC 16 - - - 2CLK 17 - - - NC 18 - - - 2D 19 - - - 2 CLR 20 - - - VCCFIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84011 DEFENSE SUPPLY C

44、ENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL G SHEET 7 DSCC FORM 2234 APR 97 Inputs Outputs PRE CLR CLK D Q Q L H X X H L H L X X L H L L X X H* H* H H H H L H H L L H H H L X Q0Q0H = High level L = Low level X = Irrelevant = Transition from low to high level Q0= The level of Q before the

45、 indicated steady-state input conditions were established * = This configuration is nonstable; that is, it will not persist when preset and clear inputs return to their inactive (high) level. FIGURE 2. Truth tables. Provided by IHSNot for ResaleNo reproduction or networking permitted without license

46、 from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84011 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL G SHEET 8 DSCC FORM 2234 APR 97 FIGURE 3. Logic diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCI

47、RCUIT DRAWING SIZE A 84011 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL G SHEET 9 DSCC FORM 2234 APR 97 NOTES: 1. CLincludes probe and jig capacitance. 2. All inputs have the following characteristics: PRR 10 MHz, duty cycle = 50 percent, tr= tf= 3 ns 1 ns. 3. The outputs

48、are measured one at a time with one input transition per measurement. FIGURE 4. Test circuit and switching waveforms - Continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84011 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL G SHEET 10 DSCC FORM 2234 APR 97 TABLE II. Electrical test requirements. MIL-STD-883 test requirements Subgroups (in accordance with MIL-STD-883, method 5005, table I) Interim electrical para