DLA SMD-5962-83002 REV H-2006 MICROCIRCUIT HYBRID LINEAR 12-BIT DIGITAL-TO-ANALOG RANGE PROGRAMMABLE VOLTAGE OUTPUT CONVERTER SILICON《硅单片12比特数字模拟可编程序输入输出转变器 线性混合微型电路》.pdf

《DLA SMD-5962-83002 REV H-2006 MICROCIRCUIT HYBRID LINEAR 12-BIT DIGITAL-TO-ANALOG RANGE PROGRAMMABLE VOLTAGE OUTPUT CONVERTER SILICON《硅单片12比特数字模拟可编程序输入输出转变器 线性混合微型电路》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-83002 REV H-2006 MICROCIRCUIT HYBRID LINEAR 12-BIT DIGITAL-TO-ANALOG RANGE PROGRAMMABLE VOLTAGE OUTPUT CONVERTER SILICON《硅单片12比特数字模拟可编程序输入输出转变器 线性混合微型电路》.pdf（13页珍藏版）》请在麦多课文档分享上搜索。

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add vendor FSCM 51640 technical and editorial changes throughout. 85-01-15 M. A. Frye B Page 2, add case outline D-3. Page 9, change eligibility requirement paragraph 3.7. Editorial changes throughout. 85-11-11 M. A. Frye C Page 4, table I, chang

2、e IIHfrom 40 A to 250 A. Change to standard military drawing format. Change code identification to 67268. Editorial changes throughout. 89-02-03 M. A. Frye D Delete vendor CAGE 13919. Package X not available from approved source. Changed to reflect MIL-H-38535 processing. Editorial changes throughou

3、t. 90-07-09 W. Heckman E Technical changes to tables I and II. Editorial changes throughout. 92-10-03 Alan Barone F Changes in accordance with NOR 5962-R213-94. 94-06-17 Kendall A. Cottongim G Table I, change limits and units for VOS, dAE/dT, and BPAE. Table I, change tSLHand tSHLto tSLand change th

4、e conditions for the test. Table I, NO test, add note 2. Table I, correct the notes for the associated tests. Update drawing boilerplate to most current format. 02-10-29 Raymond Monnin H Update drawing. 06-12-06 Raymond Monnin THE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED. CURRENT CAGE

5、CODE 67268 REV SHEET REV SHEET REV STATUS REV H H H H H H H H H H H H OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/A PREPARED BY Gary Zahn DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY William E. Shoup POST OFFICE BOX 3990 COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.m

6、il THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY N. A. Hauck MICROCIRCUIT, HYBRID, LINEAR, 12-BIT DIGITAL-TO-ANALOG RANGE PROGRAMMABLE VOLTAGE OUTPUT CONVERTER, SILCON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 82-08-09 AMSC N/A REVISION LEVEL H SIZE A CAGE CO

7、DE 14933 83002 SHEET 1 OF 12 DSCC FORM 2233 APR 97 5962-E131-07Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 83002 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL H SHEET 2 DSCC FORM 2234

8、 APR 97 1. SCOPE 1.1 Scope. This drawing documents one product assurance class, class H (high reliability), hybrid microcircuit to be processed in accordance with MIL-PRF-38534 and a choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). 1.

9、2 PIN. The PIN shall be as shown in the following example: 83002 01 J X Drawing number Device type Case outline Lead finish (see 1.2.1) (see 1.2.2) (see 1.2.3) 1.2.1 Device type(s). The device type(s) shall identify the circuit function as follows: Device type Generic number Circuit function 01 DAC

10、87 (Hybrid) D/A converter, 12-bit with output voltage ranges as follows: 0 V to +5 V unipolar 0 V to +10 V unipolar -2.5 V to +2.5 V bipolar -5 V to +5 V bipolar -10 V to +10 V bipolar 1.2.2 Case outline(s). The case outline(s) shall be as designated in MIL-STD-1835 and as follows: Outline letter De

11、scriptive designator Terminals Package style J CDIP2-T24 24 Dual-in-line X See figure 1 24 Dual-in-line 1.2.3 Lead finish. The lead finish shall be as specified in MIL-PRF-38534. 1.3 Absolute maximum ratings. Positive supply voltage VCCto digital return . 18 V dc Negative supply voltage VEEto digita

12、l return -18 V Positive supply voltage VDDto digital return . 7 V Digital input voltage to digital return. 0 V to VDDOutput short circuit duration (to ground only). 25 ms Lead temperature (soldering, 60 seconds). +300C Storage temperature range -65C to +150C Junction temperature (TJ) +175C Thermal r

13、esistance, junction-to-case (JC): Case J See MIL-STD-1835 Case X 7C/W Thermal resistance, junction-to-ambient (JA): Case J 50C/W Case X 37C/W Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 83002 DEFENSE SUPPLY CE

14、NTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL H SHEET 3 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions. Positive supply voltage range (VCC) . 14.5 V to 15.5 V Negative supply voltage range (VEE) -15.5 V to -14.5 V Positive supply voltage range (VDD) . 4.5 V to 5.5 V Ambient oper

15、ating temperature range (TA) -55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are t

16、hose cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38534 - Hybrid Microcircuits, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard for Electronic Component Case Outlines.

17、 DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Des

18、k, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulat

19、ions unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item performance requirements for device class H shall be in accordance with MIL-PRF-38534. Compliance with MIL-PRF-38534 may include the performance of all tests herein or as designated in the

20、device manufacturers Quality Management (QM) plan or as designated for applicable device class. The manufacturer may eliminate, modify or optimize the tests and inspections herein, however the performance requirements as defined in MIL-PRF-38534 shall be met for the applicable device class. In addit

21、ion, the modification in the QM plan shall not affect the form, fit, or function of the device for the applicable device class. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38534 and herein. 3.2.1 Case outline(s

22、). The case outline(s) shall be in accordance with 1.2.2 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A

23、 83002 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL H SHEET 4 DSCC FORM 2234 APR 97 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full specified

24、 operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are defined in table I. 3.5 Marking of device(s). Marking of device(s) shall be in accordance with MIL-PRF-38534. The

25、device shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers vendor similar PIN may also be marked. 3.6 Data. In addition to the general performance requirements of MIL-PRF-38534, the manufacturer of the device described herein shall maintain the electrical test data (var

26、iables format) from the initial quality conformance inspection group A lot sample, for each device type listed herein. Also, the data should include a summary of all parameters manually tested, and for those which, if any, are guaranteed. This data shall be maintained under document revision level c

27、ontrol by the manufacturer and be made available to the preparing activity (DSCC-VA) upon request. 3.7 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to supply to this drawing. The certificate of compliance (original copy) submitted to DSCC-VA s

28、hall affirm that the manufacturers product meets the performance requirements of MIL-PRF-38534 and herein. 3.8 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38534 shall be provided with each lot of microcircuits delivered to this drawing. 4. VERIFICATION 4.1 Samplin

29、g and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38534 or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. 4.2 Screening. Screening shall be i

30、n accordance with MIL-PRF-38534. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to either DSCC-VA

31、or the acquiring activity upon request. Also, the test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. (2) TAas specified in accordance with table I of method 1015 of MIL-STD-883. b. Inter

32、im and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD

33、MICROCIRCUIT DRAWING SIZE A 83002 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL H SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Limits Test Symbol Conditions 1/ -55C TA +125C unless otherwise specified Group A subgroups Device type Min Max U

34、nit Resolution 01 12 Bits Supply current from VCCICCInput bits = 0111 1111 1111, VCC= 15 V, TA= +25C 1 01 1 30 mA Supply current from VEEIEEInput bits = 0111 1111 1111, VEE= 15 V, TA= +25C 1 01 -45 -1 mA Supply current from VDDIDDInput bits = 0111 1111 1111, VDD= 5 V, TA= +25C 1 01 25 mA Input low c

35、urrent IIL VIN(logic) = 0 V, VDD= 5.5 V, VCC= 15.0 V, (each input measured separately), TA= +25C 1 01 0 +100 A Input high current IIH VIN(logic) = 5.5 V, VDD= 5.5 V, VCC= 15.0 V, (each input measured separately), TA= +25C 1 01 -1 +250 A Output short circuit current IOSCInput bits = 1111 1111 1111, T

36、A= +25C 7 2/ 01 -40 mA Reference voltage VREF IO= +200 A, TA= +25C 1 01 5.89 6.60 V Reference voltage drift dVREF dT 3/, TA= -55C and +125C 2,3 01 -20 +20 PPM/C Unipolar offset voltage error VOSInput bits = 1111 1111 1111, Unipolar, VFSR = 10 V ( Initial ) ( End-point ) TA= +25C 1 01 -0.1 -0.1 +0.1

37、+0.1 %FSR %FSR Unipolar offset voltage drift dVOS dT 3/, TA= -55C and +125C 2,3 01 -0.012 +0.012 LSB/C See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 83002 DEFENSE SUPPLY CENTER COL

38、UMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL H SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Limits Test Symbol Conditions 1/ -55C TA +125C unless otherwise specified Group A subgroups Device type Min Max Unit Gain error 4/ AE Input bits = 0000 0000 000

39、0 to input bits = 1111 1111 1111, Unipolar, VFSR = 10 V ( Initial ) ( End-point ) TA= +25C 1 01 -0.1 -0.25 +0.1 +0.25 % % Gain error drift dAEdT 3/, TA= -55C and +125C 2,3 01 -25 +25 PPM of FSR/C Bipolar gain error BPAE Input bits = 0000 0000 0000 to input bits = 1111 1111 1111, TA= +25C 5/ 1 01 -0.

40、20 +0.20 % of FSR Bipolar offset error BPOE Input bits = 1111 1111 1111, ( Initial ) ( End-point ) TA= +25C 5/ 1 01 -4 -6 +4 +6 LSB LSB Bipolar offset error drift dBPOEdT 3/, TA= -55C and +125C 2,3 2/ 01 -0.08 +0.08 LSB/C Bipolar zero error BZE Input bits = 1111 1111 1111, TA= +25C 5/ 1 2/ 01 -2 +2

41、LSB Bipolar zero error drift dBZEdT 3/, TA= -55C and +125C 2,3 01 -0.04 +0.04 LSB/C Power supply sensitivity at full scale +PSS1 Input bits = 0000 0000 0000, +14.5 V VCC +15.0 V, +15.0 V VCC +15.5 V 1,2,3 2/ 01 -0.16 -0.16 +0.16 +0.16 LSB/%PS LSB/%PS Power supply sensitivity at full scale +PSS2 Inpu

42、t bits = 0000 0000 0000, +4.5 V VDD +5.0 V, +5.0 V VDD +5.5 V 1,2,3 2/ 01 -0.16 -0.16 +0.16 +0.16 LSB/%PS LSB/%PS Power supply sensitivity at full scale -PSS Input bits = 0000 0000 0000, -15.5 V VEE 15.0 V, -15.0 V VEE -14.5 V 1,2,3 2/ 01 -0.16 -0.16 +0.16 +0.16 LSB/%PS LSB/%PS See footnotes at end

43、of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 83002 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL H SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristi

44、cs - Continued. Limits Test Symbol Conditions 1/ -55C TA +125C unless otherwise specified Group A subgroups Device type Min Max Unit Integral linearity error LE (Abbreviated codes test) 6/ (Initial) (End point) 1,2,3 01 -0.5 -1.5 +0.5 +1.5 LSB LSB Differential linearity error DLE (Abbreviated codes

45、test) 1,2,3 01 -1.0 +1.0 LSB Integral linearity error LE (All codes test) 7,8 2/ 01 -0.5 +0.5 LSB Settling time to 0.1% FSR for FSR change (2 k500 pF with 10 k feedback resistor) 9,10,11 2/ 01 5 s Settling time tSLSettling time to 0.1% FSR for FSR change (2 k500 pF with 5 k feedback resistor) 9,10,1

46、1 2/ 01 3 s Output noise voltage NO All inputs = 1111 1111 1111, 10 Hz BW 100 kHz, TA= +25C 9 2/ 01 100 V rms 1/ Unless otherwise specified, VCC= 15.0 V, VEE= -15.0 V, VDD= 5.0 V, logic “0“ = 0.8 V, logic “1“ = 2.0 V, VFSR = 20 V, -55C TA +125C, bipolar operation, load resistance RL= 2 k. 2/ These p

47、arameters in subgroups 1, 2, 3, 7, 8, 9, 10, and 11 shall be tested as part of initial characterization and after design and process changes. 3/ Calculations for dVREF/dT, dVOS/dT, dAE/dT, dBPOE/dT, and dBZE/dT are determined from measurements made at +125C, +25C, and -55C for VREF, VOS, AE, BPOE, a

48、nd BZE, respectively. 4/ The gain error of a 12-bit D/A converter in percent of full scale range corresponds to gain error in LSB units by the following relationship: 0.20 percent x 4096 LSB/100 percent = 8.92 LSB. 5/ Unless otherwise stated, all tests are performed in the bipolar mode over a -10 V to +10 V range. The scale factor is VFSR/4096 LSB (i.e., for VFSR = 20 V, the scale factor is 20 V/4096 LSB = 4.88 mV/LSB). 6/ The abbreviated integral linearity error test shown for subgroups 1, 2, and