DLA SMD-5962-77007 REV G-2005 MICROCIRCUIT DIGITAL 4-BIT MICROPROCESSOR MONOLITHIC SILICON《硅单片4比特微处理器数字微型电路》.pdf

《DLA SMD-5962-77007 REV G-2005 MICROCIRCUIT DIGITAL 4-BIT MICROPROCESSOR MONOLITHIC SILICON《硅单片4比特微处理器数字微型电路》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-77007 REV G-2005 MICROCIRCUIT DIGITAL 4-BIT MICROPROCESSOR MONOLITHIC SILICON《硅单片4比特微处理器数字微型电路》.pdf（15页珍藏版）》请在麦多课文档分享上搜索。

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED E Convert to military drawing format. Add burn-in condition C. Add vendor CAGE 50088. Editorial changes throughout. Change code ident. no. to 67268. 88-08-25 Michael A. Frye F Add device type 03. Update boilerplate. Editorial changes throughout. tv

2、n 99-04-26 Monica L. Poelking G Correct marking requirements in 3.5. Update boilerplate in accordance with MIL-PRF-38535 requirements. Editorial changes throughout. - PHN 05-02-17 Thomas M. Hess THE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED REV SHEET REV SHEET REV STATUS REV G F G G F F

3、 F F F F G G G G OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Todd D. Creek DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Ray Monnin COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Mi

4、chael A. Frye AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 77-05-17 MICROCIRCUIT, DIGITAL, 4-BIT MICROPROCESSOR, MONOLITHIC SILICON AMSC N/A SIZE A CAGE CODE 67268 77007 REVISION LEVEL G SHEET 1 OF 14 DSCC FORM 2233 APR 97 5962-E173-05 Provided by IHSNot for ResaleNo reproduction

5、or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 77007 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN cl

6、ass level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 77007 01 X X Drawing number Device type (see 1.2.1) Case outline (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device type(s). The device t

7、ype(s) identify the circuit function as follows: Device type Generic number Circuit function 01 2901A 4-bit bipolar microprocessor 02 2901 4-bit bipolar microprocessor 03 2901 4-bit bipolar microprocessor 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Ou

8、tline letter Descriptive designator Terminals Package style Q GDIP1-T40 or CDIP2-T40 40 Dual in line package Z See figure 1 42 Flat package 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Supply voltage range (VCC). -0.5 V dc to +6.3 V d

9、c Input voltage range. -0.5 V to 5.5 V Input current . -30 mA to +5 mA Output current (into outputs). 30 mA Maximum junction temperature (TJ) +150C Storage temperature range -65C to +150C Lead temperature (soldering, 5 seconds) +270C Maximum power dissipation (PD) . 1.54 W Thermal resistance, juncti

10、on-to-case (JC) Case Q. See MIL-PRF-38535 Case Z . 0.04C/mW Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 77007 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL G SHEET 3 DSCC FORM 2234 AP

11、R 97 1.4 Recommended operating conditions. Supply voltage (VCC). +4.5 V dc to +5.5 V dc Supply voltage (VSS) . 0.0 V dc Applied voltage to outputs for high state -0.5 V to VCC maximum Minimum high level input voltage (VIH) . 2.0 V dc Maximum low level input voltage (VIL) 0.7 V dc Case operating temp

12、erature range (TC) -55C to +125C Minimum read-modify-write cycle . 120 ns Minimum clock low time (tPWL) 30 ns Minimum clock high time (tPWH) 30 ns Minimum clock period (tCP) . 120 ns Maximum clock frequency to shift Q register (fC) 8.3 MHz 2. APPLICABLE DOCUMENTS 2.1 Government specification, standa

13、rds, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integra

14、ted Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-H

15、DBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In

16、 the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. Provided by IHSNot for ResaleNo reproduct

17、ion or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 77007 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL G SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance w

18、ith MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 ma

19、y be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not

20、 affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design,

21、construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.2 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.3 Electrica

22、l performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified

23、 in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. 3.5.1 Certification/compliance

24、 mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certific

25、ate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall affirm that the manuf

26、acturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of chan

27、ge. Notification of change to DSCC-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be m

28、ade available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 77007 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 5 DSCC FORM 2234 APR 97 TA

29、BLE I. Electrical performance characteristics. Limits Test Symbol Conditions -55C TC +125C unless otherwise specified Device type Group A subgroups Min Max Unit High level output voltage, Y0, Y1, Y2, Y3, G VOH1 IOH = -1.6 mA 2.4 High level output voltage, Cn+4 VOH2 IOH = -1.0 mA 2.4 High level outpu

30、t voltage, OVR, P VOH3 IOH = -800 A 2.4 High level output voltage, F3, RAM0, RAM3, Q0, Q3 VOH4 VCC = 4.5 V VIH = 2.0 V VIL = 0.7 V IOH = -600 A All 1, 2, 3 2.4 V Low level output voltage, Y0, Y1, Y2, Y3, G VOL1 IOL = 16 mA 0.5 Low level output voltage, Cn+4, F = 0 VOL2 IOL = 10 mA 0.5 Low level outp

31、ut voltage, OVR, P VOL3 IOL = 8 mA 0.5 Low level output voltage, F3, RAM0, RAM3, Q0, Q3 VOL4 VCC = 4.5 V VIH = 2.0 V VIL = 0.7 V IOL = 6 mA All 1, 2, 3 0.5 V Input clamp voltage VI VCC = 4.5 V, II = -18 mA All 1 -1.5 V Output leakage current for F = 0 output ICEX VCC = 4.5 V, VOH = 5.5 V VIH = 2.0 V

32、, VIL = 0.7 V All 1, 2, 3 250 A Short circuit output current 1/ IOS VCC = 5.5 V All 1, 2, 3 -15 -85 mA Low level input current, Clock, OE IIL1 -0.36 Low level input current, A0, A1, A2, A3 IIL2 -0.36 Low level input current, B0, B1, B2, B3 IIL3 -0.36 Low level input current, D0, D1, D2, D3 IIL4 -0.7

33、2 Low level input current, I0, I1, I2, I6, I8 IIL5 -0.36 Low level input current, I3, I4, I5, I7 IIL6 -0.72 Low level input current, RAM0, RAM3, Q0, Q3 (At high Z state) 2/ IIL7 -0.8 Low level input current, Cn IIL8 VCC = 5.5 V, VIN = 0.5 V All 1, 2, 3 -3.6 mA See footnotes at end of table. Provided

34、 by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 77007 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Li

35、mits Test Symbol Conditions -55C TC +125C unless otherwise specified Device type Group A subgroups Min Max Unit High level input current, Clock, OE IIH1 20 High level input current, A0, A1, A2, A3 IIH2 20 High level input current, B0, B1, B2, B3 IIH3 20 High level input current, D0, D1, D2, D3 IIH4

36、40 High level input current, I0, I1, I2, I6, I8 IIH5 20 High level input current, I3, I4, I5, I7 IIH6 40 High level input current, RAM0, RAM3, Q0, Q3 (At high Z state) 2/ IIH7 100 High level input current, Cn IIH8 VCC = 5.5 V, VIN = 2.7 V All 1, 2, 3 200 A Supply current ICC VCC = 5.5 V All 1, 2, 3

37、280 mA Input current at maximum input voltage II VCC = 5.5 V, VI = 5.5 V All 1, 2, 3 1 mA IOZH1 VOUT = 2.4 V 50 Off-state (high Z) output current, Y0, Y1, Y2, Y3 IOZL1 VOUT = 0.5 V -50 IOZH2 VOUT = 2.4 V 100 Off-state (high Z) output current, RAM0, RAM3, Q0, Q3 2/ IOZL2 VCC = 5.5 V VOUT = 0.5 V All

38、1, 2, 3 -800 A 01, 03 65 Propagation delay time, clock to Y 3/ tCY 02 9, 10, 11 125 ns 01, 03 65 Propagation delay time, clock to F3 tCF3 02 9, 10, 11 95 ns 01, 03 65 Propagation delay time, clock to Cn+4 tCC4 02 9, 10, 11 110 ns 01, 03 55 Propagation delay time, clock to G , P tCGP 02 9, 10, 11 110

39、 ns 01, 03 85 Propagation delay time, clock to F = 0 tCF0 VCC = 4.5 V and 5.5 V CL = 15 Pf RL = 470 (at F = 0) R = 5 k 02 9, 10, 11 120 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SI

40、ZE A 77007 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Limits Test Symbol Conditions -55C TC +125C unless otherwise specified Device type Group A subgroups Min Max Unit 01, 03 75

41、Propagation delay time, clock to OVR tCOV 02 9, 10, 11 105 ns 01, 03 85 Propagation delay time, clock to RAM tCRM 02 9, 10, 11 115 ns 01, 03 35 Propagation delay time, clock to Q tCQ 02 9, 10, 11 65 ns 01, 03 85 Propagation delay time, A, B to Y tPA1 02 9, 10, 11 120 ns 01, 03 85 Propagation delay t

42、ime, A, B to F3 tPA2 02 9, 10, 11 95 ns 01, 03 80 Propagation delay time, A, B to Cn+4 tPA3 02 9, 10, 11 90 ns 01, 03 70 Propagation delay time, A, B to G , P tPA4 02 9, 10, 11 90 ns 01, 03 100 Propagation delay time, A, B to F = 0 tPA5 02 9, 10, 11 120 ns Propagation delay time, A, B to OVR tPA6 Al

43、l 9, 10, 11 90 ns 01, 03 100 Propagation delay time, A, B to RAM tPA7 02 9, 10, 11 120 ns 01, 03 50 Propagation delay time, D to Y tPD1 02 9, 10, 11 110 ns 01, 03 50 Propagation delay time, D to F3 tPD2 02 9, 10, 11 80 ns 01, 03 50 Propagation delay time, D to Cn+4 tPD3 02 9, 10, 11 75 ns 01, 03 40

44、Propagation delay time, D to G , P tPD4 02 9, 10, 11 75 ns 01, 03 65 Propagation delay time, D to F = 0 tPD5 02 9, 10, 11 110 ns 01, 03 60 Propagation delay time, D to OVR tPD6 VCC = 4.5 V and 5.5 V CL = 15 pF RL = 470 (at F = 0) R = 5 k 02 9, 10, 11 65 ns See footnotes at end of table. Provided by

45、IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 77007 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 8 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Limits

46、 Test Symbol Conditions -55C TC +125C unless otherwise specified Device type Group A subgroups Min Max Unit 01, 03 70 Propagation delay time, D to RAM tPD7 02 9, 10, 11 105 ns 01, 03 45 Propagation delay time, Cn to Y tPC1 02 9, 10, 11 60 ns 01, 03 45 Propagation delay time, Cn to F3 tPC2 02 9, 10,

47、11 40 ns Propagation delay time, Cn to Cn+4 tPC3 All 9, 10, 11 30 ns 01, 03 55 Propagation delay time, Cn to F = 0 tPC5 02 9, 10, 11 55 ns 01, 03 35 Propagation delay time, Cn to OVR tPC6 02 9, 10, 11 45 ns 01, 03 55 Propagation delay time, Cn to RAM tPC7 02 9, 10, 11 60 ns 01, 03 60 Propagation del

48、ay time, I0, I1, I2 to Y tPI1 02 9, 10, 11 90 ns 01, 03 60 Propagation delay time, I0, I1, I2 to F3 tPI2 02 9, 10, 11 70 ns 01, 03 55 Propagation delay time, I0, I1, I2 to Cn+4 tPI3 02 9, 10, 11 70 ns 01, 03 50 Propagation delay time, I0, I1, I2 to G , P tPI4 02 9, 10, 11 70 ns 01, 03 75 Propagation delay time, I0, I1, I2 to F = 0 tPI5 02 9, 10, 11 85 ns 01, 03 70 Propagation delay time, I0, I1, I2 to OVR tPI6 02 9, 10, 11 70 ns 01, 03 80 Propagation delay time, I0, I1, I2 to RAM tPI7 02 9, 10, 11 85 ns 01, 03 60 Propagation delay time, I3, I4, I5 to Y tPJ1 02 9, 10, 11 75 ns 01, 03 60