DLA SMD-5962-12225 REV A-2013 MICROCIRCUIT DIGITAL MEMORY CMOS FIELD PROGRAMMABLE GATE ARRAY 280 000 EQUIVALENT ASIC GATES WITH INDEPENDENT SRAM MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add radiation hardness criteria for device type 01. Corrected footnote sequence for 1.5 and 1.6. Change table I to table IA. Add footnote 3 in table IA. Add table IB. Add Post column attach test CGA package information to 4.4.3 and table IIA. Add

2、 4.4.4.1 through 4.4.4.2. Update boilerplate to current MIL-PRF-38535 requirements. - lhl 13-12-09 Charles F. Saffle REV A A A SHEET 35 36 37 REV A A A A A A A A A A A A A A A A A A A A SHEET 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 REV STATUS REV A A A A A A A A A A A A A A OF SH

3、EETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Laura Turner DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A CHECKE

4、D BY Laura Turner APPROVED BY Charles F. Saffle MICROCIRCUIT, DIGITAL, MEMORY, CMOS, FIELD PROGRAMMABLE GATE ARRAY, 280,000 EQUIVALENT ASIC GATES, WITH INDEPENDENT SRAM, MONOLITHIC SILICON DRAWING APPROVAL DATE 13-05-22 REVISION LEVEL A SIZE A CAGE CODE 67268 5962-12225 SHEET 1 OF 37 DSCC FORM 2233

5、APR 97 5962-E067-14 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-12225 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing docume

6、nts two product assurance class levels consisting of high reliability (device class Q) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance

7、 (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 R 12225 01 V X B Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2) Device class designator Case outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing numbe

8、r 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Gene

9、ric number Circuit function 01 ATF280F 280k Field Programmable Gate Array 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation Q or V Certification and qualification to MIL-PRF

10、-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X See figure 1 472 Column grid Array and Solder Column Interposer Y See figure 1 472 Land grid Array Z See figure 1 352 Quad Flatpack unfo

11、rmed Leads U See figure 1 256 Quad Flatpack unformed Leads 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-12225

12、 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ 2/ Supply voltage range (VCC1) . -0.3 V to 2.0 V 3/ Supply voltage range (VCC2) . -0.3 V to 4.0 V 4/ All output voltages with respect to ground. -0.3 V to 4.0 V Maximum po

13、wer dissipation (PD). 3.3 W Case temperature range, (TC) -55C to +125C Thermal resistance, junction to case X,Y. 1C/W Z, U 2C/W Storage temperature range (Ts) -65C to +150C Maximum junction temperature (TJ) . +175C Lead temperature (soldering 10 sec) 5/ X, Y . +220C Z, U. +300C 1.4 Recommended opera

14、ting conditions. 2/ 6/ 7/ Supply voltage range (VCC1) 1.65 V to 1.95 V 3/ Supply voltage range (VCC2) 3.0 V to 3.6 V 4/ Ambient temperature (TA). -55C to 125C IO Power Supply (VCC2) 3.3 V 0.3 V LVDS I/O Power Supply (VCCB) 3.3 V 0.3 V LVDS Reference Voltage (VREF). 1.25 V 0.1 V Core Power Supply (VC

15、C1) 1.8 V 0.15 V _ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ All voltages referenced to ground unless otherwise specified. 3/ For core. 4/ For interface I/Os. 5/

16、For Multilayer Quad Flat Package case, duration 10 seconds maximum at a distance of not less than 1.6mm from the device body and the same terminal shall not be resoldered until 3 minutes have elapsed; else, during reflow. 6/ When the device needs to be powered “on/off” while other circuits in the ap

17、plication are still powered, the recommended “power on/off” sequences are: Power-up: First power VCC2 (I/O), Then power VCC1 (Core). Power-down: First unpower VCC1 (Core), Then unpower VCC2 (I/O). It is also recommended to stop all activity during these phases as a bi-directional could be in an unde

18、termined state (input or output mode) and create bus contention. 7/ Cold sparing capability of the IOs allows to be electrically connected to a bus while its power supply remains in the range VSS-300mV/VSS+300mV, this without any risk of damage for the device. Cold-sparing allows a redundant spare t

19、o be electrically connected but unpowered until needed. For applications requiring high reliability, the capability to use of a redundant device is a key feature. Cold sparing availability on the ATF280F makes the FPGA especially suitable for high reliability systems. The cold sparing feature is ava

20、ilable for all the IOs: All the General Purpose IOs All the LVDS IOs They present an high input impedance when unpowered VSS-300mV / VSS+300mV and exhibit a negligible leakage current if exposed to a non-null input voltage at that time. Provided by IHSNot for ResaleNo reproduction or networking perm

21、itted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-12225 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 4 DSCC FORM 2234 APR 97 1.5 Radiation features Maximum total dose available (dose rate = 0.083 rads(Si)/s) 100 krads(Si) 8/ Single event phenomena

22、 (SEP): Heavy ion no SEL occurs at effective LET (see 4.4.4.4) . 70 MeV-cm2/mg 9/ Proton test no SEL occurs at threshold LET (see 4.4.4.4) 7.9 MeV-cm2/mg 9/ (proton energy=230 MeV at fluence =7.4x1011 particles/cm2) 1.6 Digital logic testing for device classes Q and V. Fault coverage measurement of

23、manufacturing logic tests (MIL-STD-883, test method 5012). . 95 percent 10/ 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, th

24、e issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface S

25、tandard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/quicksearch.dla.mil or from the Standardization Document Order De

26、sk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) _ 8/ Radiation end point limits for the noted parameters are guaranteed only for the conditions as specified in MIL-STD-883, method 1019, condition B. 9/ For detailed RHA data and test information, contact the device manufacturer. 10

27、/ 95 percent test coverage of blank programmable logic devices. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-12225 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 5 DSCC FORM 2234 AP

28、R 97 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of the documents are the issues of the documents cited in the solicitation. AMERICAN SOCIETY FOR TESTING AND MATERIALS (ASTM) ASTM Stand

29、ard F1192 - Standard Guide for the Measurement of Single Event Phenomena (SEP) Induced by Heavy Ion Irradiation of Semiconductor Devices. (Applications for copies of ASTM publications should be addressed to: ASTM International, PO Box C700, 100 Barr Harbor Drive, West Conshohocken, PA 19428-2959; ht

30、tp:/www.astm.org.) JEDEC INTERNATIONAL (JEDEC) JEDEC JESD 78 - IC Latch-Up Test. (Copies of this document are available online at www.jedec.org/ or from JEDEC, 3103 North 10th Street, Suite 240-S, Arlington, VA 22201). TELECOMMUNICATIONS INDUSTRY ASSOCIATION 2001 TIA/EIA-644 - Electrical Characteris

31、tics of Low Voltage Differential Signaling (LVDS) Interface Circuits. (Copies of this document are from TELECOMMUNICATIONS INDUSTRY ASSOCIATION 2001, Standards and Technology Department, 2500 Wilson Boulevard, Arlington, VA 22201). INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS (IEEE) IEEE Standa

32、rd 1149.1 - Test Access Port and Boundary-Scan Architecture (Applications for copies should be addressed to the IEEE, 1828 L Street, N.W., Suite 1202, Washington, D.C. 20036-5104.) stds-infoieee.org (Non-Government standards and other publications are normally available from the organizations that p

33、repare or distribute the documents. These documents also may be available in or through libraries or other informational services.) 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing

34、 in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 as specified herein, or as modified in th

35、e device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein

36、 for device classes Q and V. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Block diagram. The block diagram shall be as specified on figure 3. 3.2.3.1 LVDS In

37、terface. The LVDS basic interface and bidirectional communication shall be as specified on figure 4. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-12225 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVIS

38、ION LEVEL A SHEET 6 DSCC FORM 2234 APR 97 3.2.4 Truth table(s). 3.2.4.1 Unprogrammed devices. The truth table or test vectors for unprogrammed devices for contracts involving no altered item drawing is not part of this drawing. When required in screening (see 4.2 herein) or qualification conformance

39、 inspection, groups A, B, C, D, or E (see 4.4 herein), the devices shall be programmed by the manufacturer prior to test. A minimum of 90 percent of the total number of logic modules shall be utilized. 3.2.4.2 Programmed devices. Prior to submitting altered item drawing the truth table or test vecto

40、rs for programmed devices should be agreed upon by acquiring activity and the manufacturer. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as speci

41、fied in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with

42、the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA

43、designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. 3.6 Certificate of compliance. For device class

44、es Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply for this draw

45、ing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 shall be provided with each lot of microcircuits deliv

46、ered to this drawing. 3.8 Processing options. Since the device is capable of being programmed by either the manufacturer or the user to result in a wide variety of configurations; two processing options are provided for selection in the contract. 3.8.1 Unprogrammed device delivered to the user. All

47、testing shall be verified through group A testing as defined in 4.4.1 and table IIA. 3.8.2 Manufacturer-programmed device delivered to the user. All testing requirements and quality assurance provisions herein, shall be satisfied by the manufacturer prior to delivery. Manufacturer shall verify desig

48、n checksum after programming. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-12225 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 7 DSCC FORM 2234 APR 97 TABLE IA. Electrical performance characteristics. 1/ 2/ 3/ Test Symbol Conditions 3/ -55C TA +125C 1.65V VCC1 1.95V 3.0V VCC2 3.6V Group A subgroups Device type Limits