DLA SMD-5962-07247 REV A-2013 MICROCIRCUIT DIGITAL-LINEAR 14 BIT 2 4 GSPS DIGITAL TO ANALOG CONVERTER MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Corrected maximum output update rate test, fDAC, in Table I from 2.4 min to 2.4 max. Added differential data interface section in Table I which includes Tsetup, Tholdtests. Added delay lock loop (DLL) section in Table I which includes NegD, PosD,

2、 and fDACtests. Corrected terminal connection for terminal number M14 from GND to a blank space. Added to description for terminal number M12 in figure 2. Added figures 4 and 5. Removed references to class M. -rrp 13-05-01 C. SAFFLE REV SHEET REV A A A A A A A SHEET 15 16 17 18 19 20 21 REV STATUS R

3、EV A A A A A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY RAJESH PITHADIA DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF TH

4、E DEPARTMENT OF DEFENSE CHECKED BY RAJESH PITHADIA APPROVED BY ROBERT M. HEBER MICROCIRCUIT, DIGITAL-LINEAR, 14 BIT, 2.4 GSPS DIGITAL TO ANALOG CONVERTER, MONOLITHIC SILICON DRAWING APPROVAL DATE 09-01-26 AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 67268 5962-07247 SHEET 1 OF 21 DSCC FORM 2233 APR 97

5、 5962-E340-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-07247 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents tw

6、o product assurance class levels consisting of high reliability (device class Q) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA)

7、 levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 07247 01 V X A Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2) Device class designator Case outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.

8、1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic nu

9、mber Circuit function 01 DAC5670-SP 14 bit, 2.4 GSPS digital-to-analog converter 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation Q or V Certification and qualification to

10、MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X see figure 1 192 Ceramic ball grid array 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q

11、 and V. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-07247 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ Supply voltage, AV

12、DDto GND 5.0 V DA_P130, DA_N130, DB_P130, DB_N130 . -0.3 V min to AVDD+ 0.3 V max 2/ NORMAL, A_ONLY, A_ONLY_INV, A_ONLY_ZS -0.3 V min to AVDD+ 0.3 V max 2/ DTCLK_P, DTCLK_N, DACCLK_P, DACCLK_N -0.3 V min to AVDD+ 0.3 V max 2/ LVDS_HTB, INV_CLK, RESTART -0.3 V min to AVDD+ 0.3 V max 2/ IOUT_P, IOUT_N

13、 AVDD 0.5 V min to AVDD+ 0.3 V max 2/ CSCAP_IN, REFIO_IN, RBIAS_IN -0.3 V min to AVDD+ 0.3 V max 2/ Total power dissipation (PD) 2350 mW Peak input current (any input) 20 mA Peak total input current (all inputs) -30 mA Storage temperature range (TSTG) . -65C to +150C Lead temperature 1.6 mm (1/16 in

14、ch) from the case for 10 seconds +260C Thermal resistance, junction-to-ambient (JA) . 41.3C/W Thermal resistance, junction-to-case (JC) 3.8C/W 1.4 Recommended operating conditions. Operating case temperature range (TC) . -55C to +125C Estimated device life at elevated temperatures electromigration f

15、ail modes: _ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Measured with respect to GND. Provided by IHSNot for ResaleNo reproduction or networking permitted without

16、license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-07247 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 4 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks fo

17、rm a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENS

18、E STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are ava

19、ilable online at https:/assist.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this d

20、rawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 as specif

21、ied herein, or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as speci

22、fied in MIL-PRF-38535 and herein for device classes Q and V. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Block diagram. The block diagram shall be as specif

23、ied on figure 3. 3.2.5 Radiation exposure circuit. The radiation exposure circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing and acquiring activity upon request. 3.3 Electrical performance characteristics and postirradia

24、tion parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements sha

25、ll be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not fe

26、asible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. 3.5.1 Certification/compliance mark. T

27、he certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-07247 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REV

28、ISION LEVEL A SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ -55C TC +125C Group A subgroups Device type Limits Unit unless otherwise specified Min Max Resolution 1,2,3 All 14 Bits DC accuracy section Integral nonlinearity INL fDAC= 640 kHz,

29、fOUT= 10 kHz 1,2,3 All -7.5 7.5 LSB Differential nonlinearity DNL 1,2,3 -0.98 1.75 LSB Monotonocity 1,2,3 All 14 Bits Analog output section Offset error Mid code offset 1,2,3 All -0.45 0.45 %FSR Gain error With external reference 1,2,3 All -6.0 6.0 %FSR With internal reference 1,2,3 -6.0 6.0 %FSR Fu

30、ll scale output current IOFS1,2,3 All 30 mA Output compliance range IO(FS)= 20 mA, AVDD= 3.15 V to 3.45 V 1,2,3 All AVDD- 0.5 AVDD+ 0.5 V Reference output section Reference voltage VREF1,2,3 All 1.14 1.26 V Reference input section Input voltage range VREFIO1,2,3 All 1.14 1.26 V Power supply section

31、Analog supply voltage AVDD1,2,3 All 3 3.6 V Analog supply current IAVDDfDAC = 2.4 GHz, NORMAL input mode 1,2,3 All 650 mA Sleep mode, AVDDsupply current IAVDDSleep mode (SLEEP pin high) 1,2,3 All 180 mA Power dissipation PDfDAC = 2.4 GHz, NORMAL input mode 1,2,3 All 2350 mW Power supply rejection ra

32、tio PSRR AVDD= 3.15 V to 3.45 V 1,2,3 All 1.3 %FSR/ V See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-07247 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEE

33、T 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics continued. Test Symbol Conditions 1/ -55C TC +125C Group A subgroups Device type Limits Unit unless otherwise specified Min Max Analog output section Maximum output update rate fDAC4,5,6 All 2.4 GSPS AC performance section Spu

34、rious free dynamic range SFDR fDAC= 2.4 GSPS, fOUT= 100 MHz, dual port mode, 0 dBFS 4,5,6 All 46 dBc fDAC= 2.4 GSPS, fOUT= 300 MHz, dual port mode, 0 dBFS 4,5,6 31 fDAC= 2.4 GSPS, fOUT= 500 MHz, dual port mode, 0 dBFS 4,5,6 35 Signal-to-noise ratio SNR fDAC= 2.4 GSPS, fOUT= 100 MHz, dual port mode,

35、0 dBFS 4,5,6 All 58 dBc fDAC= 2.4 GSPS, fOUT= 300 MHz, dual port mode, 0 dBFS 4,5,6 56 fDAC= 2.4 GSPS, fOUT= 500 MHz, dual port mode, 0 dBFS 4,5,6 51 Total harmonic distortion THD fDAC= 2.4 GSPS, fOUT= 100 MHz, dual port mode, 0 dBFS 4,5,6 All 45 dBc fDAC= 2.4 GSPS, fOUT= 300 MHz, dual port mode, 0

36、dBFS 4,5,6 31 fDAC= 2.4 GSPS, fOUT= 500 MHz, dual port mode, 0 dBFS 4,5,6 35 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-07247 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-399

37、0 REVISION LEVEL A SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics continued. Test Symbol Conditions 1/ -55C TC +125C Group A subgroups Device type Limits Unit unless otherwise specified Min Max AC performance section - continued Third order tow tone intermodulation IMD

38、3 fDAC= 2.4 GSPS, fOUT= 253 MHz and 257 MHz, each tone at -6 dBFS, dual port mode 4,5,6 All 47 dBc fDAC= 2.4 GSPS, fOUT= 299 MHz and 302 MHz, each tone at -6 dBFS, dual port mode 4,5,6 35 Four tone intermodulation IMD fDAC= 2.4 GSPS, fOUT= 298 MHz, 299 MHz, 300 MHz, and 301 MHz. Each tone at -12 dBF

39、S, dual port mode 4,5,6 All 47 dBc Digital characteristics CMOS interface (SLEEP, RESTART, INV_CLK, NORMAL, A_ONLY, A_ONLY_INV, A_ONLY_ZS) High level input voltage VIH1,2,3 All 2 V Low level input voltage VIL1,2,3 All 0 0.8 V High level input current IIH1,2,3 All 10 A Low level input current IIL1,2,

40、3 All -10 A Differential data interface (DA_P13:0, DA_N13:0, DB_P13:0, DB_N13:0, DTCLK_P, DTCLK_N) Differential input threshold VITH1,2,3 All -100 100 mV Internal termination impedance ZT1,2,3 All 80 125 Input common mode VICOM1,2,3 All 0.6 1.4 V Differential data interface (DA_P13:0, DA_N13:0, DB_P

41、13:0, DB_N13:0, DTCLK_P, DTCLK_N External timing with DLL in restart) Data setup to DLYCLK 2/ tsetupRESTART = 1, DLYCLK 20 pF load, see figure 4 9,10,11 All 2.45 ns Data hold to DLYCLK 2/ tholdRESTART = 1, DLYCLK 20 pF load, see figure 4 9,10,11 All -1.2 ns See footnotes at end of table. Provided by

42、 IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-07247 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 8 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics continued. Test Symbol

43、 Conditions 1/ -55C TC +125C Group A subgroups Device type Limits Unit unless otherwise specified Min Max Digital characteristics - continued Clock inputs (DACCLK_P, DACCLK_N) Clock differential input voltage VCLKTH1,2,3 All 200 1000 mV Clock duty cycle 9,10,11 All 40 60 % Clock common mode VCLKCM1,

44、2,3 All 1.0 1.4 V Delay lock loop (DLL) See figure 5 DLL minimum negative delay NegD RESTART = 0 9,10,11 150 DLL minimum positive delay PosD RESTART = 0 9,10,11 600 Maximum output update rate fDACRESTART = 0 4,5,6 All 1 2.4 GHz 1/ Unless otherwise specified, AVDD= 3 V to 3.6 V, IOUT(FS)= 20 mA. 2/ T

45、ested using signal to noise ratio (SNR) as pass/fail criteria. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). The certificate of c

46、ompliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein. 3.7 Certificate of conformance. A certificate of conformance

47、as required for device classes Q and V in MIL-PRF-38535 shall be provided with each lot of microcircuits delivered to this drawing. 4. VERIFICATION 4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with MIL-PRF-38535 or as modified in

48、the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. 4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted on all devices prior to qualification and technology conformance inspection. Provided by IHSNot for ResaleNo reproduction or networking permitted without li