DLA DSCC-VID-V62-04743-2005 MICROCIRCUIT LINEAR LOW POWER LOW OFFSET QUAD VOLTAGE COMPARATORS MONOLITHIC SILICON《微型电路 线形 低功率 低偏移 四倍电压比较器 单块硅》.pdf
《DLA DSCC-VID-V62-04743-2005 MICROCIRCUIT LINEAR LOW POWER LOW OFFSET QUAD VOLTAGE COMPARATORS MONOLITHIC SILICON《微型电路 线形 低功率 低偏移 四倍电压比较器 单块硅》.pdf》由会员分享,可在线阅读,更多相关《DLA DSCC-VID-V62-04743-2005 MICROCIRCUIT LINEAR LOW POWER LOW OFFSET QUAD VOLTAGE COMPARATORS MONOLITHIC SILICON《微型电路 线形 低功率 低偏移 四倍电压比较器 单块硅》.pdf(12页珍藏版)》请在麦多课文档分享上搜索。
1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV REV STATUS OF PAGES PAGE 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/A PREPARED BY RICK OFFICER DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing YY-MM-DD
2、CHECKED BY TOM HESS APPROVED BY RAYMOND MONNIN TITLE MICROCIRCUIT, LINEAR, LOW POWER, LOW OFFSET, QUAD VOLTAGE COMPARATORS, MONOLITHIC SILICON SIZE A CODE IDENT. NO. 16236 DWG NO. V62/04743 05-03-07 REV PAGE 1 OF 12 AMSC N/A 5962-V028-05 Provided by IHSNot for ResaleNo reproduction or networking per
3、mitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04743 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance low power, low offset, quad voltage comparators microcircuit, with an
4、operating temperature range of -40C to +85C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/04743 - 01 X A
5、Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 LM2901EP Low power, low offset, quad voltage comparators 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Number of
6、pins JEDEC PUB 95 Package style X 14 M0-012-AB Plastic small outline Y 14 See figure 1 Plastic dual in line 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture: Finish designator Material A Hot solder dip B Tin-lead plate C Gold
7、plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04743 REV PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage (
8、+V) . 36 V dc or 18 V dc Differential input voltage 36 V dc 2/ Input voltage -0.3 V dc to +36 V dc Input current (VIN -0.3 V dc) . 50 mA 3/ Power dissipation (PD) : 4/ Case X (small outline package) 760 mW Case Y (molded dual in line package) 1050 mW Output short circuit to GND Continuous 5/ Storage
9、 temperature range (TSTG) . -65C to +150C Lead temperature (soldering, 10 seconds) +260C Operating temperature range (TA) . -40C to +85C Soldering information: Case X (vapor phase, 60 seconds) 215C (infared, 15 seconds) . 220C Case Y (soldering, 10 seconds) . 260C Electrostatic discharge (ESD) ratin
10、g (1.5 k in series with 100 pF) . 600 V 1.4 Recommended operating conditions. 6/ Operating temperature range (TA) -40C to +85C 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the devi
11、ce at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ Positive excursions of input voltage may exceed the power supply level. As long as
12、other remains within the common mode range, the comparator will provide a proper output state. The low input voltage state must not be less than -0.3 V dc (or 0.3 V dc below the magnitude of the negative power supply, if used) (at 25C). 3/ This input current will only exist when the voltage at any o
13、f the input leads is driven negative. It is due to the collector-base junction of the input PNP transistors becoming forward biased and thereby acting as input diode clamps. In addition to this diode action, there is also lateral NPN parasitic transistor action on the IC chip. This transistor action
14、 can cause the output voltages of the comparators to go to the +V voltage level (or to ground for a large overdrive) for the time duration that an input is driven negative. This is not destructive and normal output state will re-establish when the input voltage, which was negative, again returns to
15、a value greater than -0.3 V dc (at 25C). 4/ For operating at high temperatures, the device must be derated based on a 125C maximum junction temperature and a thermal resistance of 95C/W which applies for the device soldered in a printed circuit board, operating in a still air ambient. The low bias d
16、issipation and the “ON OFF” characteristic of the outputs keeps the chip dissipation very small (PD 100 mW), provided the output transistors are allowed to saturate. 5/ Short circuits from the output to +V can cause excessive heating and eventual destruction. When considering short circuits to groun
17、d, the maximum output current is approximately 20 mA independent of the magnitude of +V. 6/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond th
18、e stated limits. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04743 REV PAGE 4 2. APPLICABLE DOCUMENTS JEDEC PUB 95 Registered and Standard Outlines for Semicon
19、ductor Devices (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown
20、in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The ma
21、ximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outlines. The
22、case outlines shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDEN
23、T NO. 16236 DWG NO. V62/04743 REV PAGE 5 TABLE I. Electrical performance characteristics. 1/ Limits Test Symbol Conditions +V = 5 V dc unless otherwise specifiedTemperature, TA Device type Min Max Unit Input offset voltage VIO2/ +25C 01 7.0 mV dc 2.0 typical Input bias current IIBIIN(+)or IIN(-)with
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