DLA DSCC-VID-V62 12661 REV A-2013 MICROCIRCUIT DIGITAL-LINEAR 18 BIT VOLTAGE OUTPUT DIGITAL TO ANALOG CONVERTER MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Delete all Daisy chain references under SCLK cycle time test and footnote 14/ as specified under Table I. Delete figure 5, Daisy chain mode timing diagram. - ro 13-10-03 C. SAFFLE Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV A A

2、A PAGE 18 19 20 REV STATUS OF PAGES REV A A A A A A A A A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PMIC N/A PREPARED BY RICK OFFICER DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil/ Original date of drawing YY-MM-DD CHECKED BY RAJESH PITHADIA T

3、ITLE MICROCIRCUIT, DIGITAL-LINEAR, 18 BIT, VOLTAGE OUTPUT DIGITAL TO ANALOG CONVERTER, MONOLITHIC SILICON 13-06-18 APPROVED BY CHARLES F. SAFFLE SIZE A CODE IDENT. NO. 16236 DWG NO. V62/12661 REV A PAGE 1 OF 20 AMSC N/A 5962-V086-13 Provided by IHSNot for ResaleNo reproduction or networking permitte

4、d without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12661 REV A PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance 18 bit, voltage output digital to analog converter (DAC) microcircuit, with an oper

5、ating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/12661 - 01 X B Dra

6、wing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 AD5781 18 bit, voltage output digital to analog converter 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pi

7、ns JEDEC PUB 95 Package style X 20 MO-153-AC Thin shrink small outline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palla

8、dium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12661 REV A PAGE 3 1.3 Absolute maximum ratings. 1/ 2/ Positive analog supply voltage (VDD) to analog ground ref

9、erence (AGND) -0.3 V to +34 V Negative analog supply (VSS) to AGND -34 V to +0.3 V VDDto VSS. -0.3 V to +34 V Digital supply voltage (VCC) to digital ground reference (DGND) -0.3 V to +7 V Digital interface supply (IOVCC) to DGND -0.3 V to VCC+ 3 V or +7 V (whichever is less) Digital inputs to DGND

10、-0.3 V to IOVCC+ 0.3 V or +7 V (whichever is less) Analog output voltage (VOUT) to AGND -0.3 V to VDD+ 0.3 V Positive reference force voltage (VREFPF) to AGND -0.3 V to VDD+ 0.3 V Positive reference sense voltage (VREFPS) to AGND . -0.3 V to VDD+ 0.3 V Negative reference force voltage (VREFNF) to AG

11、ND . VSS 0.3 V to + 0.3 V Negative reference sense voltage (VREFNS) to AGND . VSS 0.3 V to +0.3 V DGND to AGND -0.3 V to +0.3 V Storage temperature range (TSTG) -65C to +150C Maximum junction temperature range (TJ) +150C Power dissipation (PD) 120 mW Electrostatic discharge (ESD): Human body model (

12、HBM) 1.5 kV 1.4 Recommended operating conditions. 3/ Operating free-air temperature range (TA) . -55C to +125C 1.5 Thermal characteristics. Thermal resistance, junction to case (JC) 45C/W Thermal resistance, junction to ambient (JA) . 143C/W 1/ Stresses beyond those listed under “absolute maximum ra

13、ting” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods ma

14、y affect device reliability. 2/ Unless otherwise specified, TA= +25C. Transient currents of up to 100 mA do not cause silicon controlled rectifier (SCR) latch up. 3/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or dist

15、ributor maintain no responsibility or liability for product used beyond the stated limits. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12661 REV A PAGE 4 2. APPLICABLE D

16、OCUMENTS JEDEC Solid State Technology Association JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 3. REQUIREME

17、NTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the man

18、ufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The des

19、ign, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Timing waveforms. The timing waveforms shall be as

20、 shown in figures 3 and 4. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12661 REV A PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions 2/ 3

21、/Temperature, TA Device type Limits Unit Min Max Static performance 4/ Resolution -55C to +125C 01 18 Bits Integral nonlinearity error (relative accuracy) VREFP= +10 V, VREFN= -10 V -55C to +125C 01 -0.5 +0.5 LSB 0.25 typical VREFP= +10 V, VREFN= 0 V 5/ -0.5 +0.5 0.25 typical VREFP= +5 V, VREFN= 0 V

22、 5/ -1 +1 0.5 typical Differential nonlinearity error VREFP= +10 V, VREFN= -10 V -55C to +125C 01 -0.5 +0.5 LSB 0.25 typical VREFP= +10 V, VREFN= 0 V -0.5 +0.5 0.25 typical VREFP= +5 V, VREFN= 0 V -1 +1 0.5 typical Linearity error long 6/ term stability After 500 hours +125C 01 0.04 typical LSB Afte

23、r 1,000 hours 0.05 typical After 1,000 hours +100C 0.03 typical Full scale error FSE VREFP= +10 V, VREFN= -10 V 5/ -55C to +125C 01 -1.75 +1.75 LSB 0.25 typical VREFP= +10 V, VREFN= 0 V 5/ -2.75 +2.75 0.062 typical VREFP= +5 V, VREFN= 0 V 5/ -5.25 +5.25 0.2 typical See footnotes at end of table. Pro

24、vided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12661 REV A PAGE 6 TABLE I. Electrical performance characteristics Continued. 1/ Test Symbol ConditionsTemperature, TA Device ty

25、pe Limits Unit Min Max Static performance continued. 4/ Full scale error FSE VREFP= +10 V, VREFN= -10 V 5/ 0C to +105C 01 -1 +1 LSB 0.25 typical VREFP= +10 V, VREFN= 0 V 5/ -1 +1 0.062 typical VREFP= +5 V, VREFN= 0 V 5/ -1.5 +1.5 0.2 typical Full scale error temperature coefficient +25C 01 0.02 typi

26、cal ppm FSR/ C Zero scale error ZSE VREFP= +10 V, VREFN= -10 V 5/ -55C to +125C 01 -1.75 +1.75 LSB 0.025 typical VREFP= +10 V, VREFN= 0 V 5/ -2.5 +2.5 0.38 typical VREFP= +5 V, VREFN= 0 V 5/ -5.25 +5.25 0.19 typical VREFP= +10 V, VREFN= -10 V 5/ 0C to +105C -1 +1 0.025 typical VREFP= +10 V, VREFN= 0

27、 V 5/ -1 +1 0.38 typical VREFP= +5 V, VREFN= 0 V 5/ -1.5 +1.5 0.19 typical See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12661 REV A PAGE 7

28、TABLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions 2/ 3/Temperature, TA Device type Limits Unit Min Max Static performance continued. 4/ Zero scale error 5/ temperature coefficient +25C 01 0.04 typical ppm FSR/ C Gain error AE VREFP= +10 V, VREFN= -10 V 5/ -55C to +

29、125C 01 -6 +6 ppm FSR 0.3 typical VREFP= +10 V, VREFN= 0 V 5/ -10 +10 0.4 typical VREFP= +5 V, VREFN= 0 V 5/ -20 +20 0.4 typical Gain error 5/ temperature coefficient +25C 01 0.04 typical ppm FSR/ C R1, RFB matching +25C 01 0.01 typical % Output characteristics 5/ Output voltage range +25C 01 VREFNV

30、REFPV Output slew rate Unbuffered output, 10 M|20 pF load 7/ +25C 01 50 typical V/s Output voltage settling time 10 V step to 0.02%, using AD845 buffer in unity gain mode +25C 01 1 typical s 125 code step to 1 LSB 8/ 1 typical Output noise spectral density At 1 kHz, DAC code = midscale +25C 01 7.5 t

31、ypical nV / At 10 kHz, DAC code = midscale 7.5 typical Hz At 100 kHz, DAC code = midscale 7.5 typical Output voltage noise DAC code = midscale, 9/ 0.1 Hz to 10 Hz bandwidth +25C 01 1.1 typical VPPSee footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted with

32、out license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12661 REV A PAGE 8 TABLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions 2/ 3/Temperature, TA Device type Limits Unit Min Max Output characteristics - continued. 5/ Mi

33、dscale glitch 10/ impulse VREFP= +10 V, VREFN= -10 V 5/ +25C 01 3.1 typical nV- sec VREFP= +10 V, VREFN= 0 V 5/ 1.7 typical VREFP= +5 V, VREFN= 0 V 5/ 1.4 typical MSB segment 10/ glitch impulse VREFP= +10 V, VREFN= -10 V 5/ +25C 01 9.1 typical nV- sec VREFP= +10 V, VREFN= 0 V 5/ 3.6 typical VREFP= +

34、5 V, VREFN= 0 V 5/ 1.9 typical Output enabled glitch impulse On removal of output ground clamp +25C 01 45 typical nV-sec Digital feedthrough +25C 01 0.4 typical nV-sec DC output impedance (normal mode) +25C 01 3.4 typical k DC output impedance (output clamped to ground) +25C 01 6 typical k Spurious

35、free dynamic range 1 kHz tone, 10 kHz sample rate +25C 01 100 typical dB Total harmonic distortion 1 kHz tone, 10 kHz sample rate +25C 01 97 typical dB Reference inputs 5/ VREFPinput range -55C to +125C 01 5 VDD 2.5 V VREFNinput range -55C to +125C 01 VSS+ 2.5 V 0 DC input impedance VREFP, VREFN, co

36、de dependent, -55C to +125C 01 5 k typical mid-scale code 6.6 typical Input capacitance CINVREFP, VREFN+25C 01 15 typical pF See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CO

37、DE IDENT NO. 16236 DWG NO. V62/12661 REV A PAGE 9 TABLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions 2/ 3/Temperature, TA Device type Limits Unit Min Max Logic inputs 5/ Input current 11/ IIN-55C to +125C 01 -1 +1 A Input low voltage VILIOVCC= 1.71 V to 5.5 V -55C t

38、o +125C 01 0.3 x IOVCCV Input high voltage VIHIOVCC= 1.71 V to 5.5 V -55C to +125C 01 0.7 x IOVCCV Pin capacitance +25C 01 5 typical pF Logic output (SDO) 5/ Output low voltage VOLIOVCC= 1.71 V to 5.5 V, sinking 1 mA -55C to +125C 01 0.4 V Output high voltage VOHIOVCC= 1.71 V to 5.5 V, sourcing 1 mA

39、 -55C to +125C 01 IOVCC 0.5 V V High impedance leakage current -55C to +125C 01 1 A High impedance output capacitance +25C 01 3 typical pF Power requirements. All digital inputs at DGND or IOVCCPositive analog supply voltage VDD-55C to +125C 01 7.5 VSS+ 33 V Negative analog supply voltage VSS-55C to

40、 +125C 01 VDD- 33 -2.5 V Digital supply voltage VCC-55C to +125C 01 2.7 5.5 V Digital interface supply voltage IOVCCIOVCC VCC-55C to +125C 01 1.71 5.5 V Positive analog supply current IDD-55C to +125C 01 5.2 mA 4.2 typical Negative analog supply current ISS-55C to +125C 01 4.9 mA 4 typical See footn

41、otes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12661 REV A PAGE 10 TABLE I. Electrical performance characteristics Continued. 1/ Test Symbol Condition

42、sTemperature, TA Device type Limits Unit Min Max Power requirements - continued. All digital inputs at DGND or IOVCCDigital supply current ICC-55C to +125C 01 900 A 600 typical Digital interface supply current IOICCSDO disabled -55C to +125C 01 140 A 52 typical DC power 5/ 12/ supply rejection ratio

43、 VDD 10%, VSS= 15 V +25C 01 0.6 typical V/V VSS 10%, VDD= 15 V 0.6 typical AC power 5/ 12/ supply rejection ratio VDD 200 mV, 50 Hz/60 Hz, VSS= -15 V +25C 01 95 typical dB VSS 200 mV, 50 Hz/60 Hz, VDD= 15 V 95 typical Timing requirements. 13/ SCLK cycle time 14/ t1IOVCC= 1.71 V to 3.3 V -55C to +125

44、C 01 40 ns IOVCC= 3.3 V to 5.5 V 28 SCLK cycle time (readback mode) IOVCC= 1.71 V to 3.3 V -55C to +125C 01 92 ns IOVCC= 3.3 V to 5.5 V 60 SCLK high time t2IOVCC= 1.71 V to 3.3 V -55C to +125C 01 15 ns IOVCC= 3.3 V to 5.5 V 10 SCLK low time t3IOVCC= 1.71 V to 3.3 V -55C to +125C 01 9 ns IOVCC= 3.3 V

45、 to 5.5 V 5 SYNC to SCLK falling edge setup time t4IOVCC= 1.71 V to 3.3 V -55C to +125C 01 5 ns IOVCC= 3.3 V to 5.5 V 5 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE ID

46、ENT NO. 16236 DWG NO. V62/12661 REV A PAGE 11 TABLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions 2/ 3/Temperature, TA Device type Limits Unit Min Max Timing requirements. 13/ SCLK falling edge to SYNC rising edge hold time t5IOVCC= 1.71 V to 3.3 V -55C to +125C 01 2

47、 ns IOVCC= 3.3 V to 5.5 V 2 Minimum SYNC high time t6IOVCC= 1.71 V to 3.3 V -55C to +125C 01 48 ns IOVCC= 3.3 V to 5.5 V 40 SYNC rising edge to next SCLK falling edge ignore t7IOVCC = 1.71 V to 3.3 V -55C to +125C 01 8 ns IOVCC = 3.3 V to 5.5 V 6 Data setup time t8IOVCC = 1.71 V to 3.3 V -55C to +125C 01 9 ns IOVCC = 3.3 V to 5.5 V 7 Data hold time t9IOVCC = 1.71 V to 3.3 V -55C to +125C 01 12 ns IOVCC = 3.3 V to 5.5 V 7 LDAC falling ed