DLA DSCC-VID-V62 12652-2013 MICROCIRCUIT DIGITAL 4O RON 4-CHANNEL 5 V +12 V V iCMOS MULTIPLEXERS MONOLITHIC SILICON.pdf
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1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE 18 REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PMIC N/A PREPARED BY Phu H. Nguyen DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritim
2、e.dla.mil/ Original date of drawing YY MM DD CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL, 4 RON, 4-CHANNEL 15 V/+12 V/5 V iCMOS MULTIPLEXERS, MONOLITHIC SILICON 13-01-22 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/12652 REV PAGE 1 OF 18 AMSC N/A 5962-V043-13 Provided
3、 by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12652 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance 4 RON, 4-/8-channel 15 V/+
4、12 V/5 V iCMOS multiplexers microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on
5、 the engineering documentation: V62/12652 - 01 X B Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 ADG1409-EP 4 RON, 4-channel 15 V/+12 V/5 V iCMOS multiplexers 1.2.2 Case outline(s). The case outli
6、nes are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 16 JEDEC MO-153-AB Think Shrink Small Outline Package 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot
7、solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12652 REV PAGE 3 1.3 Absolute maximum rat
8、ings. 1/ VDDto VSS35 V VDDto GND . -0.3 V to +25 V VSSto GND +0.3 V to -25 V Analog inputs, Digital inputs VSS-0.3 V to VDD+ 0.3 V or 30 mA, whichever occurs first 2/ Peak current, S or D 350 mA (Pulsed at 1 ms, 10% duty cycle maximum) Operating temperature range: . -55C to +125C Storage temperature
9、 range . -65C to 150C Junction temperature . 150C JA 150.4 C/W JC 50 C/W Lead temperature soldering: Vapor phase (60 sec) 215C Infrared (15 sec) 220C Continuous current per channel, S or D See table below + 10% Test Test conditions Limits Unit 25C 55C 125C Continuous current, S or D 3/ 15 V dual sup
10、ply VDD= +13.5 V, VSS= -13.5 V 140 85 45 mA max 12 V dual supply VDD= 10.8 V, VSS= 0 V 120 75 40 5 V dual supply VDD= +4.5 V, VSS= -4.5 V 115 70 40 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEP95 Registered and Standard Outlines for Semiconductor Devices (Copies of the
11、se documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201.) 1/ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings onl
12、y, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 2/ Over voltages at A, EN, S, or D will be clam
13、ped by internal diodes. Current should be limited to the maximum ratings given. 3/ Guaranteed by design, not subject to production test Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 D
14、WG NO. V62/12652 REV PAGE 4 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The uni
15、t container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, const
16、ruction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Terminal f
17、unction. The terminal function shall be as shown in figure 3. 3.5.4 Truth table. The truth table shall be as shown in figure 4. 3.5.5 Functional block diagram. The functional block diagram shall be as shown in figure 5. 3.5.6 On resistance. The On resistance shall be as shown in figure 6. 3.5.7 Off
18、leakage. The Off leakage shall be as shown in figure 7. 3.5.8 On leakage. The On leakage shall be as shown in figure 8. 3.5.9 Address to output switching times, tTRANSITION. The address to output switching times, tTRANSITIONshall be as shown in figure 9. 3.5.10 Break before make time delay, tBBM. Th
19、e break before make time delay, tBBMshall be as shown in figure 10. 3.5.11 Enable delay, tON(EN), tOFF(EN). The Enable delay, tON(EN), tOFF(EN) shall be as shown in figure 11. 3.5.12 Charge Injection. The charge Injection shall be as shown in figure 12. 3.5.13 Off isolation. The Off isolation shall
20、be as shown in figure 13. 3.5.14 Channel to Channel crosstalk. The Channel to Channel crosstalk shall be as shown in figure 14. 3.5.15 Insertion loss. The Insertion loss shall be as shown in figure 15. 3.5.16 THD + Noise. The THD + Noise shall be as shown in figure 16. Provided by IHSNot for ResaleN
21、o reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12652 REV PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Test conditions 15 V Dual Supply 2/ Limits Unit +25C -55C to +125C Min Typ
22、 Max Min Typ Max Analog switch Analog signal range VSSVDDV On Resistance RONVS= 10 V, IS= -10 mA, See FIGURE 6 VDD = +13.5 V, VSS= -13.5 V 4 4.7 6.7 On resistance match between channels RONVS= 10 V, IS= -10 mA 0.2 0.78 1.1 On resistance Flatness RFLAT(ON)VS= 10 V, IS= -10 mA 0.5 0.72 0.92 Leakage cu
23、rrents (VDD= +16.5 V, VSS= -16.5 V) Source off leakage IS(Off) VS= 10 V, VD= 10 V; See FIGURE 7 0.04 nA 0.2 5 Drain off leakage ID(Off) VS= 10 V, VD= 10 V; See FIGURE 7 0.04 0.45 30 Channel On leakage ID, IS (On) VS= VD= 10 V, See FIGURE 8 0.1 1.5 30 Digital inputs Input high voltage VIH2.0 V Input
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