DLA DSCC-VID-V62 12639-2012 MICROCIRCUIT LINEAR 15 MHz RAIL TO RAIL DUAL OPERATIONAL AMPLIFIER MONOLITHIC SILICON.pdf
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1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 PMIC N/A PREPARED BY Phu H. Nguyen DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil/ Original d
2、ate of drawing YY MM DD CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, LINEAR, 15 MHz, RAIL TO RAIL, DUAL OPERATIONAL AMPLIFIER, MONOLITHIC SILICON 12-10-12 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/12639 REV PAGE 1 OF 11 AMSC N/A 5962-V010-13 Provided by IHSNot for ResaleNo
3、reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12639 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance 15 MHz, rail to rail, dual operational amplifier m
4、icrocircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentatio
5、n: V62/12639 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 OP262-EP 15 MHz. rail to rail, dual operational amplifier 1.2.2 Case outline(s). The case outlines are as specified herein. Outl
6、ine letter Number of pins JEDEC PUB 95 Package style X 8 JEDEC MS-012-AA Standard Small Outline Package 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold pla
7、te D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12639 REV PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage . 6 V Input vo
8、ltage 6 V 2/ Differential input voltage 0.6 V 3/ Internal power dissipation SOIC (S) Observe derating curves Output short circuit duration Observe derating curves Operating temperature range: . -55C to +125C Storage temperature range . -65C to +150C Junction temperature range -65C to +150C Lead temp
9、erature range (Soldering, 10 sec) 300C 1.4 Thermal characteristics. Thermal resistance Case outline JA 4/ JCUnit Case X 157 56 C/W 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEP95 Registered and Standard Outlines for Semiconductor Devices (Copies of these documents are
10、available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201.) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A.
11、Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 1/ Stresses beyond those listed under “absolute maximum ratings” may ca
12、use permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect dev
13、ice reliability. 2/ For supply voltage greater than 6 V, the input voltage is limited to less than or equal to the supply voltage. 3/ For differential input voltages greater than 0.6 V, the input current should be limited to less than 5 mA to prevent degradation or destruction of the input device. 4
14、/ JAis specified for the worst case conditions, that is, JAis specified for a device soldered in circuit board for SOIC package. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO.
15、V62/12639 REV PAGE 4 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3 and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as spec
16、ified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND
17、 MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12639 REV PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Test conditions VS= 5.0 V, VCM= 0 V TA= 25C unless otherwise specified Limits Unit Min Typ Max Input characteristics Offset voltage VOS45 325 V -55C TA +1
18、25C 1 mV Input bias current IS360 600 nA -55C TA +125C 650 Input offset current IOS2.5 25 -55C TA +125C 40 Input voltage range VCM0 4 V Common mode rejection CMRR 0 V VCM 4.0 V, -55C TA +125C 70 110 dB Large signal voltage gain AVORL= 2 k, 0.5 V VOUT 4.5 V 30 V/mV RL= 10 k, 0.5 V VOUT 4.5 V 65 88 RL
19、= 10 k, -55C TA +125C 40 Offset voltage drift 2/ VOS/T 1 V/C Bias current drift IB/T 250 pA/C Output characteristics Output voltage swing high VOHIL= 250 A, -55C TA +125C 4.95 4.99 V IL= 5 mA 4.85 4.94 Output voltage swing low VOLIL= 250 A, -55C TA +125C 14 50 mV IL= 5 mA 65 150 Short circuit curren
20、t ISCShort to ground 80 mA Maximum output current IOUT30 Power supply Power supply rejection ratio PSRR VS= 2.7 V to 7 V 120 dB -55C TA +125C 90 Supply current/Amplifier ISYVOUT= 2.5 V 500 700 A -55C TA +125C 850 Dynamic performance Slew rate SR 1 V VOUT 4 V, RL= 10 k 10 V/s Settling time tSTo 0.1%,
21、 AV= -1, VO= 2 V step 540 ns Gain bandwidth product GBP 15 MHz Phase margin m61 Degrees Noise performance Voltage noise enp-p 0.1 Hz to 10 Hz 0.5 V p-p Voltage noise density enf = 1 kHz 9.5 nV/Hz Current noise density inf = 1 kHz 0.4 pA/Hz See footnote at end of table. Provided by IHSNot for ResaleN
22、o reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12639 REV PAGE 6 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Test conditions VS= 3.0 V, VCM= 0 V TA= 25C unless otherwise s
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