DLA DSCC-VID-V62 08628 REV A-2013 MICROCIRCUIT DIGITAL QUAD CHANNEL 14 BIT 125 MSPS ADC WITH SERIAL LVDS OUTPUT MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Add device type 02. Update boilerplate paragraphs to current requirements. - PHN 13-05-28 Thomas M. Hess CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Ve

2、ndor item drawing REV PAGE REV A A A PAGE 18 19 20 REV STATUS OF PAGES REV A A A A A A A A A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PMIC N/A PREPARED BY Phu H. Nguyen DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO Original date of drawing YY MM DD CHECKED BY Phu H. Nguyen TIT

3、LE MICROCIRCUIT, DIGITAL, QUAD CHANNEL, 14 BIT, 125 MSPS ADC WITH SERIAL LVDS OUTPUT, MONOLITHIC SILICON 08-10-21 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/08628 REV A PAGE 1 OF 20 AMSC N/A 5962-V064-13 Provided by IHSNot for ResaleNo reproduction or networking permitted wi

4、thout license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/08628 REV A PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance quad channel, 14 bit, 125 MSPS ADC with serial LVDS outputs microcircuit for

5、device type 01 and a quad channel, 14 bit, 105 MSPS ADC with serial LVDS outputs microcircuit for device type 02, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing

6、establishes an administrative control number for identifying the item on the engineering documentation: V62/08628 - 01 X A Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 ADS6445-EP Quad channel, 14

7、 bit, 125 MSPS ADC with serial LVDS outputs 02 ADS6444-EP Quad channel, 14 bit, 105 MSPS ADC with serial LVDS outputs 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins Package style X 64 Plastic quad flatpack 1.2.3 Lead finishes. The lead finishes are as

8、 specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other 1.3 Absolute maximum ratings. 1/ Supply voltage range: ADVDD . -0.3 V to 3.9 V LVDD . -0.3 V to 3.9 V V

9、oltage between AGND and DGND -0.3 V to 0.3 V Voltage between AVDD to LVDD -0.3 V to 3.3 V Voltage applied to external pin, VCM -0.3 V to 2.0 V Voltage applied to analog input pins .-0.3 V to minimum (3.6, AVDD + 0.3) V Operating junction temperature range, TJ. 150C Storage temperature range, TSTG-65

10、C to 150C Lead temperature 1.6 mm (1/16”) from the case for 10 seconds 220C 1/ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those i

11、ndicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMB

12、US, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/08628 REV A PAGE 3 1.4 Thermal characteristics. Thermal metric 2/ Case outline X Units Junction to ambient thermal resistance, JA3/ 23.6 C/W Junction to case (top) thermal resistance, JCtop4/ 7.7 Junction to board thermal resistance, JB5/ 3 Junction t

13、o top characterization parameter, JT6/ 0.1 Junction to board characterization parameter, JB7/ 3 Junction to case (bottom) thermal resistance, JCbot8/ 0.3 1.5 Recommended operating conditions. SUPPLIES Analog supply voltage, AVDD . 3.0 V to 3.6 V LVDS buffer supply voltage, LVDD 3.0 V to 3.6 V ANALOG

14、 INPUTS Differential input voltage range2.0 VP-PTypical Input common-mode voltage . 1.5 V 0.1 Typical Voltage applied on VCM in external reference mode 1.45 V to 1.55 V CLOCK INPUTS Input clock sample rate, Fsrated: Device type 01 5 to 125 MSPS Device type 02 5 to 105 MSPS Input clock amplitude diff

15、erential (VCLKP VCLKM): Minimum sine wave, ac coupled 0.4 VP-PLVPECL, ac coupled . 0.8 VP-P Typical LVDS, ac coupled 0.35 VP-P Typical LVCMOS, ac coupled 3.3 VP-P Typical Input clock duty cycle 35% to 65% DIGITAL INPUTS Maximum external load capacitance from each output pin to DGND, CLOAD: Without i

16、nternal termination . 5 pF Typical With internal termination 10 pF Typical Differential load resistance (external) between the LVDS output pairs, RLOAD100 Typical _ 3/ For more information about traditional and new thermal metrics, see manufacturer data. 4/ The junction to ambient thermal resistance

17、 under natural convection is obtained in a simulation on a JEDEC-standard, high-K-board, as specified in JESD51-7, in an environment described in JESD51-2a. 5/ The junction to case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specified JEDEC- standard t

18、est exists, but a close description can be found in the ANSI SEMI standard G30-88. 6/ The junction to board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. 7/ The junction to top characterization

19、parameter, JT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7). 8/ The junction to board characterization parameter, JB, estimates the junction temperature of a dev

20、ice in a real system and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7). 9/ The junction to case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specified JEDEC- standard test

21、exists, but a close description can be found in the ANSI SEMI standard G30-88 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/08628 REV A PAGE 4 2. APPLICABLE DOCU

22、MENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEP95 Registered and Standard Outlines for Semiconductor Devices JESD51 Methodology for the Thermal Measurement of Component Packages (Single Semiconductor Device). JESD51-2a Integrated Circuits Thermal Test Method Environment Conditions Natural

23、 Convection (Still Air) JESD51-7 High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages JESD51-8 Integrated Circuits Thermal Test Method Environment Conditions Junction-to-board (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State

24、 Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201-2107). AMERICAN NATIONAL STANDARDS INSTITUTE (ANSI) STANDARD ANSI SEMI STANDARD G30-88 null Test Method for Junction-to-Case Thermal Resistance Measurements for Ceramic Packages (Applications for copies should be addres

25、sed to the American National Standards Institute, Semiconductor Equipment and Materials International, 1819 L Street, NW, 6 th floor, Washington, DC 20036 or online at http:/www.ansi.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as

26、 shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics.

27、 The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline

28、. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Terminal description. The terminal description shall be as shown in figure 3. 3.5.4 Functional block diagram. The functional block diagram shall be as

29、 shown in figure 4. 3.5.5 Latency. The latency shall be as shown in figure 5. 3.5.6 LVDS timing. The LVDS timing shall be as shown in figure 6. 3.5.7 Reset timing. The Reset timing shall be as shown in figure 7. 3.5.8 Serial interface timing. The serial interface timing shall be as shown in figure 8

30、. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/08628 REV A PAGE 5 TABLE I. Electrical performance characteristics. 1/ 2/ Test Symbol Device type 01 Fs= 125 MSPS

31、 Device type 02 Fs= 105 MSPS Unit Min TYP Max Min TYP Max Resolution 14 14 Bits Analog input Differential input voltage range 2.0 2.0 VPPDifferential input capacitance 7 7 pF Analog input bandwidth 500 500 MHz Analog input common mode current (per input pin of each ADC) 155 130 A Reference voltages

32、Internal reference bottom voltage VREFB 1.0 1.0 v Internal reference top voltage VREFT 2.0 2.0 V Internal reference error (VREFT-VREFB) VREF0.985 1 1.015 0.985 1 1.015 V Common mode output voltage VCM 1.5 1.5 V VCM output current capability 4 4 mA DC accuracy No missing code Assured Assured Offset e

33、rror, across devices and across channels within a device EO-15 2 15 -15 2 15 mV Offset error temperature coefficient, across devices and across channels within a device 0.05 0.05 mV/C There are two source of gain error internal reference inaccuracy and channel gain error Gain error due to internal r

34、eference inaccuracy alone, (VREF/2.0)% EGREF-0.75 0.1 0.75 -0.75 0.1 0.75 %FS Reference gain error temperature coefficient 0.0125 0.0125 %/C Gain error of channel alone, across devices and across channels within a device EGCHAN0.3 0.3 %FS Channel gain error temperature coefficient, across devices an

35、d across channels within a device 0.005 0.005 %/C Differential nonlinearity, Fin = 50 MHz DNL -0.99 0.6 2.0 -0.99 0.6 2.0 LSB Integral nonlinearity, Fin = 50 MHz INL -5 3 5 -5 3 5 LSB DC power supply rejection ratio PSRR 0.5 0.5 mV/V Power supply Total supply current ICC502 410 mA Analog supply curr

36、ent IAVDD410 322 mA LVDS supply current ILVDD92 88 mA Total power 1.65 1.8 1.35 1.5 W Power down (within input clock stopped) 77 150 77 150 mW See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUM

37、BUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/08628 REV A PAGE 6 TABLE I. Electrical performance characteristics Continued. Test Symbol Conditions 2/ unless otherwise specified Device type 01 Fs= 125 MSPS Device type 02 Fs= 105 MSPS Unit Min TYP Max Min TYP Max Dynamic AC characteristic

38、s Signal to noise ratio SNR Fin = 10 MHz 73.7 73.8 dBFS Fin = 50 MHz 68.5 73.1 73.2 Fin = 70 MHz 72.7 69 73 Fin = 100 MHz 72.1 72.2 Fin = 170 MHz 0 dB gain 69.9 70.2 3.5 dB Coarse gain 69.4 69.7 Fin =230 MHz 0 dB gain 68.7 68.8 3.5 dB Coarse gain 68.1 68.2 Signal to noise and distortion ratio SINAD

39、Fin = 10 MHz 73.4 73.4 dBFS Fin = 50 MHz 67.75 72.3 71.7 Fin = 70 MHz 71.2 68.5 72 Fin = 100 MHz 71.8 72 Fin = 170 MHz 0 dB gain 67.9 69.8 3.5 dB Coarse gain 68.3 69.3 Fin =230 MHz 0 dB gain 67.8 67.7 3.5 dB Coarse gain 67.9 67.6 Output noise RMS Inputs tied to common-mode 1.05 1.05 LSB Spurious fre

40、e dynamic range SFDR Fin = 10 MHz 87 91 dBc Fin = 50 MHz 69 81 80 Fin = 70 MHz 78 74 81 Fin = 100 MHz 86 88 Fin = 170 MHz 0 dB gain 76 79 3.5 dB Coarse gain 79 83 Fin =230 MHz 0 dB gain 77 77 3.5 dB Coarse gain 80 80 Second harmonic HD2 Fin = 10 MHz 93 94 dBc Fin = 50 MHz 69 87 88 Fin = 70 MHz 87 74

41、 88 Fin = 100 MHz 89 90 Fin = 170 MHz 0 dB gain 83 84 3.5 dB Coarse gain 85 86 Fin =230 MHz 0 dB gain 80 81 3.5 dB Coarse gain 82 83 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMB

42、US, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/08628 REV A PAGE 7 TABLE I. Electrical performance characteristics Continued. Test Symbol Conditions 2/ unless otherwise specified Device type 01 Fs= 125 MSPS Device type 02 Fs= 105 MSPS Unit Min TYP Max Min TYP Max Dynamic AC characteristics - contin

43、ued Third harmonic HD3 Fin = 10 MHz 87 91 dBc Fin = 50 MHz 69 81 80 Fin = 70 MHz 78 74 81 Fin = 100 MHz 86 88 Fin = 170 MHz 0 dB gain 76 79 3.5 dB Coarse gain 79 83 Fin =230 MHz 0 dB gain 77 77 3.5 dB Coarse gain 80 80 Worst harmonic (other than HD2, HD3) Fin = 10 MHz 91 91 dBc Fin = 50 MHz 87 87 Fi

44、n = 100 MHz 90 91 Fin = 170 MHz 88 88 Fin = 230 MHz 87 87 Total harmonic distortion THD Fin = 10 MHz 86 89.5 dBc Fin = 50 MHz 69 80 80 Fin = 100 MHz 84.5 72 79 Fin = 170 MHz 73.5 86 Fin = 230 MHz 74 77 Effective number of bits ENOB Fin = 50 MHz 10.95 11.7 Bits Fin = 70 MHz 11.3 11.7 2-Tone inter-mod

45、ulation distortion IMD F1 = 46.09 MHz, F2 = 50.09 MHz 88 90 dBFS F1 = 185.09 MHz, F2 = 190.09 MHz 86 88 Cross talk Near channel Cross talk signal frequency = 10 MHz 90 92 dBc Far channel Cross talk signal frequency = 10 MHz 103 105 Input overload recovery Recovery to within 1% (of final value) for 6

46、-dB overload with sine wave input 1 1 Clock cysles Power supply rejection ratio AC PSRR DC 20 MHz SEN to SCLK setup time tSLOADS25 ns SCLK to SEN hold time tSLOADH25 SDATA setup time tDSU25 SDATA hold time tDH25 Time taken for register write to take effect after 16thSCLK falling edge 100 RESET TIMIN

47、G Power on delay time t1Delay from power-up of AVDD and LVDD to RESET pulse active 5 ms Reset pulse width t2Pulse width of active RESET signal 10 ns Register writer delay time t3Delay from RESET disable to SEN active 25 ns Power up delay time tPODelay from power-up of AVDD and LVDD to output stable

48、6.5 ms 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ Typical values are at 25C, min an