DLA DSCC-VID-V62 07605 REV A-2011 MICROCIRCUIT LINEAR DUAL OPERATIONAL AMPLIFIER MONOLITHIC SILICON.pdf
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1、 REVISIONSLTR DESCRIPTION DATE APPROVEDA Make addition to paragraph 2. Make change to to the min limit of dimension “c” and notes specified under figure 1. Update boilerplate paragraph to current requirements. - ro 11-11-14 C. SAFFLE CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA
2、LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV A A A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 10 11 PMIC N/A PREPARED BY RICK OFFICER DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 Original dat
3、e of drawing YY-MM-DD CHECKED BY TOM HESS TITLE MICROCIRCUIT, LINEAR, DUAL OPERATIONAL AMPLIFIER, MONOLITHIC SILICON 06-11-13 APPROVED BY RAYMOND MONNIN SIZE A CODE IDENT. NO. 16236 DWG NO. V62/07605 REV A PAGE 1 OF 11 AMSC N/A 5962-V004-12 Provided by IHSNot for ResaleNo reproduction or networking
4、permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/07605 REV A PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance dual operational amplifier microcircuit, with an operating temper
5、ature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/07605 - 01 X E Drawing Device
6、type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 LM258A-EP Dual operational amplifier1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 8
7、MS-012-AA Plastic surface mount1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture: Finish designator Material A Hot solder dip B Tin-lead plateC Gold plateD PalladiumE Gold flash palladium Z Other Provided by IHSNot for ResaleNo
8、 reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/07605 REV A PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage range (VDD) . 16.5 V or 32 V 2/ Differential input voltage (VID) 32 V 3/ Input
9、voltage (VI) (either input) . -0.3 V to 32 V Duration of output short circuit (one amplifier) to ground at (or below) 25C free-air temperature (VCC 15 V) Unlimited 4/ Package thermal impedance (JA) . 97C/W 5/ 6/ Operating virtual junction temperature (TJ) +150C Storage temperature range (TSTG) -65C
10、to +150C 7/ 1.4 Recommended operating conditions. 8/ Supply voltage range (VCC) . 5 V Operating free-air temperature range (TA) . -55C to +125C 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional oper
11、ation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ All voltage values, except differential voltages and VCCspecified
12、for measurement of IOS, are with respect to the network ground terminal. 3/ Differential voltages are at IN+ with respect to IN-. 4/ Short circuits from outputs to VCCcan cause excessive heating and eventual destruction. 5/ Maximum power dissipation is a function of TJ(max), JA, and TA. The maximum
13、allowable power dissipation at any allowable ambient temperature is PD= ( TJ(max) TA) / JA. Operating at the absolute maximum TJof 150C can affect reliability. 6/ The package thermal impedance is calculated in accordance with JESD 51-7. 7/ Long term high temperature storage and/or extended use at ma
14、ximum recommended operating conditions may result in a reduction of overall device life. See manufacturers datasheet or additional information on enhanced plastic packaging. 8/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer
15、and/or distributor maintain no responsibility or liability for product used beyond the stated limits. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/07605 REV A P
16、AGE 4 2. APPLICABLE DOCUMENTS JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices EIA/JEDEC 51-7 High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Applications for copies should be addressed to the JEDEC Office, 3103 North 10th Street, Suite 240-S,
17、 Arlington, VA 22201-2107 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optio
18、nal) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and t
19、able I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as sho
20、wn in figure 2. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/07605 REV A PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions 2/ VC
21、C= 5 V unless otherwise specified Temperature, TADevice type Limits Unit Min Max Input offset voltage VIOVCC= 5 V to 30 V, 25C 01 3 mV VIC= VICR(min), VO= 1.4 V -55C to +125C 4 Average temperature coefficient of input offset voltage VIO-55C to +125C 01 15 V/C Input offset current IIOVO= 1.4 V 25C 01
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