DLA DSCC-VID-V62 06673 REV A-2012 MICROCIRCUIT LINEAR LOW DROP OUT VOLTAGE REGULATORS MONOLITHIC SILICON.pdf
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1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Make changes to the following Table I tests. Output voltage test column, delete “10 mA” and replace with “1 mA”. Change the min limit from “1.71” to “1.705” and the change the max limit from “1.89” to “1.895”. Output voltage line regulation test column, del
2、ete (DVO/VO) and replace with (Vout/Vin). Minimum input voltage for valid PG test, conditions column, delete “100 mA” and replace with “100 A”. PG trip threshold voltage test, change the temperature range from “-55C to +125C” to “+25C”, delete the min and max limits and replace with “90 typical”. PG
3、 output low voltage test, conditions column, delete “100 mA” and replace with “100 A”. Update boilerplate paragraphs to current requirements. - ro 12-04-24 C. SAFFLE CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance w
4、ith ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV A A A A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/A PREPARED BY RICK OFFICER DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing YY-MM-DD CHECKED BY TOM HESS TITLE MICROCIRCUIT, L
5、INEAR, LOW DROP OUT VOLTAGE REGULATORS, MONOLITHIC SILICON 06-09-19 APPROVED BY RAYMOND MONNIN SIZE A CODE IDENT. NO. 16236 DWG NO. V62/06673 REV A PAGE 1 OF 12 AMSC N/A 5962-V021-12 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENT
6、ER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06673 REV A PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance low drop out voltage regulator microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing
7、Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/06673 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See
8、1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Voltage Circuit function 01 TPS79718-EP 1.8 V Low drop out voltage regulator 02 TPS79730-EP 3.0 V Low drop out voltage regulator 03 TPS79733-EP 3.3 V Low drop out voltage regulator 1.2.2 Case outline(s). The case outline(s) are as specifie
9、d herein. Outline letter Number of pins JEDEC PUB 95 Package style X 5 MO-203-AA Plastic small outline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate
10、 D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06673 REV A PAGE 3 1.3 Absolute maximum ratings. 1/ Input voltage range
11、 (VI) 0.3 V to 6 V 2/ Maximum dc output voltage . 4.9 V Peak output current Internally limited Electrostatic discharge rating: Human body model (HBM) . 3 kV Charged device model (CDM) 1 kV Continuous total power dissipation . See 1.5, dissipation rating table Operating junction temperature range (TJ
12、) -55C to +145C Storage temperature range (TSTG) -65C to +150C 1.4 Recommended operating conditions. 3/ Operating free-air temperature range (TA) . -55C to +125C 1.5 Dissipation ratings table. Package Board RJCRJADerating factor above TA= 25C TA 25C power rating TA= 70C power rating TA= 85C power ra
13、ting TA= 125C power rating Case X Low K 4/ 165.39C/W 396.24C/W 2.52 mW/C 252 mW 139 mW 101 mW 0 mW High K 5/ 165.39C/W 314.74C/W 3.18 mW/C 318 mW 175 mW 127 mW 127 mW 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings on
14、ly, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ All voltage values are with respect to netw
15、ork ground terminals. 3/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. 4/ The JEDEC Low-K (1s) board design used to deriv
16、e this data was a 3 inch x 3 inch, two layer board with 2 ounce copper traces on top of the board. 5/ The JEDEC High-K (2s2p) board design used to derive this data was a 3 inch x 3 inch, multilayer board with 1 ounce internal power and ground planes and 2 ounce copper traces on the top and bottom of
17、 the board. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06673 REV A PAGE 4 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION JEDEC PUB 95 Regist
18、ered and Standard Outlines for Semiconductor Devices (Applications for copies should be addressed to the JEDEC Office, 3103 North 10th Street, Suite 240-S, Arlington, VA 22201-2107 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the m
19、anufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3
20、Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 D
21、iagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Block diagram. The block diagram shall be as shown in figure 3. 3.5.4 Timing waveforms. The timing waveforms shall be as sh
22、own in figure 4. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06673 REV A PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol ConditionsTempe
23、rature, TA Device type Limits Unit Min Max Input voltage 2/ VIIO= 3 mA -55C to +125C All 1.8 5.5 V IO= 10 mA 2 5.5 Continuous output 3/ current IO-55C to +125C All 0 10 mA Operating ambient temperature TAAll -55 +125 C Output voltage 4/ VO2.8 V VI 5.5 V +25C 01 1.8 typical V (1 mA to 10 mA load) TJ=
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