DLA DSCC-VID-V62 06620 REV A-2013 MICROCIRCUIT DIGITAL QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Update boilerplate to current MIL-PRF-38535 requirements. - PHN 13-12-11 Thomas M. Hess CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing

2、 REV PAGE REV PAGE REV STATUS OF PAGES REV A A A A A A A A PAGE 1 2 3 4 5 6 7 8 PMIC N/A PREPARED BY Phu H. Nguyen DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO Original date of drawing YY MM DD CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL, QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE, MONOLITHIC SI

3、LICON 06-04-12 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/06620 REV A PAGE 1 OF 8 AMSC N/A 5962-V023-14 .Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 162

4、36 DWG NO. V62/06620 REV A PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance quadruple 2-input EXCLUSIVE-OR gate microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers

5、 PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/06620 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device

6、type Generic Circuit function 01 CD74ACT86-EP Quadruple 2-input EXCLUSIVE-OR gate 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 14 MS-012 Plastic small outline 1.2.3 Lead finishes. The lead finishes are as specified below

7、 or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other 1.3 Absolute maximum ratings. 1/ Supply voltage range ( VCC) -0.5 V to 6 V Maximum input clamp current ( IIK) ( VIVCC)

8、. 20 mA 2/ Maximum output clamp current ( IOK) (VOVCC) . 50 mA 2/ Maximum continuous output current ( IO) ( VO= 0 to VCC) . 50 mA Continuous current through VCCor GND . 100 mA Package thermal impedance ( JA) . 86C/W 3/ Storage temperature range (TSTG) . -65C to 150C _ 1/ Stresses beyond those listed

9、 under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated condit

10、ions for extended periods may affect device reliability. 2/ The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 3/ The package thermal impedance is calculated in accordance with JESD 51-7. Provided by IHSNot for ResaleNo reproduction or networki

11、ng permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06620 REV A PAGE 3 1.4 Recommended operating conditions. 4/ Supply voltage range ( VCC) 4.5 V to 5.5 V Minimum high level input voltage ( VIH) 2.0 V Maximum low level inpu

12、t voltage ( VIL) . 0.8 V Input voltage ( VI) 0 V to VCCOutput voltage ( VO) 0 V to VCCMaximum high level output current ( IOH) . -24 mA Maximum low level output current ( IOL) . 24 mA Maximum input transition rise or fall rate ( t / v ) 10 ns/V 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY AS

13、SOCIATION (JEDEC) JEP95 Registered and Standard Outlines for Semiconductor Devices (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201-2107). 3. REQUIREMENTS 3.1 Marking. Part

14、s shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part numbe

15、r and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, an

16、d physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Function table. The Function table shall be as shown in figure 3. 3.5.4

17、 Logic diagram. The logic diagram shall be as shown in figure 4. 3.5.5 Load circuit and voltage waveforms. The load circuit and voltage waveforms shall be as shown in figure 5. 4/ All unused inputs of the device must be held at VCCor GND to ensure proper device operation. Provided by IHSNot for Resa

18、leNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06620 REV A PAGE 4 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions- VCCLimits Unit TA= 25C -55C TA 125C Min Max Min

19、 Max High level output voltage VOHVI= VIHor VILIOH= -50 A 4.5 V 4.4 4.4 V IOH= -24 mA 3.94 3.7 IOH= -50 mA 1/ 5.5 V 3.85 3.85 Low level output voltage VOLVI= VIHor VILIOL= 50 A 4.5 V 0.1 0.1 V IOL= 24 mA 0.36 0.5 IOL= 50 mA 1/ 5.5 V 1.65 1.65 Input current IIVI= VCCor GND 5.5 V 0.1 1 A Supply curren

20、t ICCVI= VCCor GND, IO= 0, 5.5V 4 80 A Supply current change 2/ ICCVIor VO= 0 to 5.5 V 4.5 V to 5.5 V 2.4 3 mA Input capacitance CiVI= VCCor GND 10 10 pF Power dissipation capacitance Cpd5.0 V 57 Typ Propagation delay time, from input A or B to output Y tPLH4.5 V to 5.5 V 3.7 14.6 ns tPHL3.7 14.6 1/

21、 Test one output at a time, not exceeding 1-s duration. Measurement is made by forcing indicated current and measuring voltage to minimize power dissipation. Test verifies a minimum 50 transmission line drive capability at 85C and 75 transmission line drive capability at 125C 2/ Additional quiescent

22、 supply current per input pin, TTL inputs high, 1 unit load ACT input load table Input Unit Load All 0.48 Unit load is ICC limit specified in electrical characteristic table (e.g., 2.4 mA at 25C) Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENS

23、E SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06620 REV A PAGE 5 Case X Dimension Symbol Millimeters Inches Symbol Millimeters Inches Min Max Min Max Min Max Min Max A 1.75 0.069 E 3.80 4.00 0.150 0.157 A1 0.10 0.25 0.004 0.010 E1 5.80 6.20 0.228 0.244 b 0.31 0.51

24、0.012 0.020 e 1.27 NOM 0.050 NOM c 0.17 0.25 0.007 0.010 L 0.40 1.27 0.016 0.050 D 8.55 8.75 0.337 0.344 NOTES: 1. This drawing is subject to change without notice. 2. Body dimensions do not include mold flash or protrusion not to exceed 0.15 mm (0.006 inches). 3. Falls within JEDEC MS-012 variation

25、 AB. FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06620 REV A PAGE 6 Case X Terminal number Terminal symbol Terminal number Terminal sym

26、bol 1 1A 8 3Y 2 1B 9 3A 3 1Y 10 3B 4 2A 11 4Y 5 2B 12 4A 6 2Y 13 4B 7 GND 14 VCCFIGURE 2. Terminal connections. Input Output Y A B L L L L H H H L H H H L FIGURE 3. Function table. Five equivalent exclusive-OR symbols Notes: 1. The output is active (low) if all inputs stand at the same logic level (

27、i.e., A = B). 2. The output is active (low) if an even number of inputs (i.e., 0 or 2) are active. 3. The output is active (high) if an odd number of inputs (i.e., only 1 of the 2) are active. FIGURE 4. Logic diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without licen

28、se from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06620 REV A PAGE 7 NOTES: 1. CLincludes probe and test fixture capacitance. 2. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output co

29、ntrol. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. 3. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO= 50 ,tr= 3 ns, and tf= 3 ns. Phase relationships between waveforms a

30、re arbitrary. 4. For clock inputs, fmaxis measured with the input duty cycle at 50%. 5. The outputs are measured one at a time with one input transition per measurement. 6. tPHLand tPLHare the same as tpd. 7. tPZLand tPZHare the same as ten. 8. tPLZand tPHZare the same as tdis. 9. All parameters and

31、 waveforms are not applicable to all devices. FIGURE 5. Load circuit and voltage waveforms Continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06620 REV A P

32、AGE 8 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, an

33、d labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturers standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are

34、 electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturers data book. The device manufacturer reserves the right to make changes without notice. This drawing w

35、ill be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of

36、all current sources of supply at http:/www.landandmaritime.dla.mil/Programs/Smcr/. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Vendor part number Top side marking V62/06620-01XE 01295 CD74ACT86MDREP ACT86MEP 1/ The vendor item drawing establishes an administrat

37、ive control number for identifying the item on the engineering documentation. CAGE code Source of supply 01295 Texas Instruments, Inc. Semiconductor Group 8505 Forest lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-