DLA DSCC-VID-V62 06609 REV A-2013 MICROCIRCUIT DIGITAL ADVANCED BIPOLAR CMOS 16-BIT BUS TRANSCEIVER WITH THREE-STATE OUTPUTS MONOLITHIC SILICON.pdf
《DLA DSCC-VID-V62 06609 REV A-2013 MICROCIRCUIT DIGITAL ADVANCED BIPOLAR CMOS 16-BIT BUS TRANSCEIVER WITH THREE-STATE OUTPUTS MONOLITHIC SILICON.pdf》由会员分享,可在线阅读,更多相关《DLA DSCC-VID-V62 06609 REV A-2013 MICROCIRCUIT DIGITAL ADVANCED BIPOLAR CMOS 16-BIT BUS TRANSCEIVER WITH THREE-STATE OUTPUTS MONOLITHIC SILICON.pdf(11页珍藏版)》请在麦多课文档分享上搜索。
1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Update boilerplate to current MIL-PRF-38535 requirements. - PHN 13-12-11 Thomas M. Hess CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing
2、 REV PAGE REV PAGE REV STATUS OF PAGES REV A A A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 10 11 PMIC N/A PREPARED BY Charles F. Saffle DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing CHECKED BY Charles F. Saffle TITLE MICROCIRCUIT, DIGITAL, ADVANCED BIPOLAR CMOS, 16-B
3、IT BUS TRANSCEIVER WITH THREE-STATE OUTPUTS, MONOLITHIC SILICON YY-MM-DD 06-01-17 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/06609 REV A PAGE 1 OF 11 AMSC N/A 5962-V020-14 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFEN
4、SE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06609 REV A PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance 16-bit bus transceiver with three-state outputs microcircuit, with an operating temperature range of -55C to
5、+125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/06609 - 01 X E Drawing Device type Case outline Lead
6、finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 SN74ABT16245A-EP 16-bit bus transceiver with three-state outputs 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package styl
7、e X 48 JEDEC MO-118 Plastic small-outline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other 1.3 Absolute max
8、imum ratings. 1/ Supply voltage range (VCC) . -0.5 V to +7 V Input voltage range (except I/O ports) (VI) -0.5 V to +7 V 2/ Voltage applied to any output in the high or power-off state (VO) -0.5 V to +5.5 V Maximum current into any output in the low state (IO) . 96 mA Maximum input clamp current (VI
9、0) (IIK) -18 mA Maximum output clamp current (VO 0) (IOK) -50 mA Package thermal impedance (JA) . 94C/W 3/ Storage temperature range (TSTG) . -65C to 150C 4/ _ 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and
10、 functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ The input and output negative-voltage ratings may
11、be exceeded if the input and output clamp-current ratings are observed. 3/ The package thermal impedance is calculated in accordance with JESD 51. 4/ Long-term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of overall device life. S
12、ee figure 1 for additional information on thermal derating. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06609 REV A PAGE 3 1.4 Recommended operating conditions
13、. 1/ Supply voltage range (VCC) . 4.5 V to 5.5 V Minimum high-level input voltage (VIH) 2 V Maximum low-level input voltage (VIL) . 0.8 V Input voltage range (VI) . 0 V to VCCMaximum high-level output current (IOH) . -24 mA Maximum low-level output current (IOL) . 48 mA Maximum input transition rise
14、 or fall rate (Outputs enabled) (t/v) 10 ns/V Minimum power-up ramp rate (t/VCC) 200 s/V Operating free-air temperature range (TA) -55C to +125C FIGURE 1. Estimated device life at elevated temperatures. 1/ All unused inputs of the device must be held at VCCor GND to ensure proper device operation. P
15、rovided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06609 REV A PAGE 4 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEP95 Registered and Sta
16、ndard Outlines for Semiconductor Devices (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201-2107). 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked
17、with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) a
18、bove. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified her
19、ein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 2. 3.5.2 Function table. The function table shall be as shown in figure 3. 3.5.3 Logic diagram. The logic diagram shall be as shown in figure 4. 3.5.4 Terminal connections. The terminal connections shall be
20、 as shown in figure 5. 3.5.5 Timing waveforms and test circuit. The timing waveforms and test circuit shall be as shown in figure 6. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO.
21、16236 DWG NO. V62/06609 REV A PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions VCCTemperature, TALimits Unit Min Max Input clamp voltage VIKII= -18 mA 4.5 V 25C -1.2 V -55C to +125C -1.2 High level output voltage VOHIOH= -3 mA 4.5 V 25C, -55C to +125C 2.5 V IOH= -3 m
22、A 5 V 25C, -55C to +125C 3 IOH= -24 mA 4.5 V 25C, -55C to +125C 2 IOH= -32 mA 25C 2 Low level output voltage VOLIOL= 48 mA 4.5 V 25C, -55C to +125C 0.55 V IOL= 64 mA 25C 0.55 Hysteresis voltage Vhys5 V 25C 100 TYP mV Input current IIControl inputs, VI= VCCor GND 0 V to 5.5 V 25C, -55C to +125C 1 A A
23、 or B port, VI= VCCor GND 2.1 V to 5.5 V 25C 20 -55C to +125C 100 Three-state output current, power-up IOZPUVO= 0.5 V to 2.7 V, OE= X 0 V to 2.1 V 25C 50 A Three-state output current, power-down IOZPDVO= 0.5 V to 2.7 V, OE= X 2.1 V to 0 V 25C 50 A Three-state output current, high IOZH2/ VO= 2.7 V, O
- 1.请仔细阅读文档,确保文档完整性,对于不预览、不比对内容而直接下载带来的问题本站不予受理。
- 2.下载的文档,不会出现我们的网址水印。
- 3、该文档所得收入(下载+内容+预览)归上传者、原创作者;如果您是本文档原作者,请点此认领!既往收益都归您。
下载文档到电脑,查找使用更方便
10000 积分 0人已下载
下载 | 加入VIP,交流精品资源 |
- 配套讲稿:
如PPT文件的首页显示word图标,表示该PPT已包含配套word讲稿。双击word图标可打开word文档。
- 特殊限制:
部分文档作品中含有的国旗、国徽等图片,仅作为作品整体效果示例展示,禁止商用。设计者仅对作品中独创性部分享有著作权。
- 关 键 词:
- DLADSCCVIDV6206609REVA2013MICROCIRCUITDIGITALADVANCEDBIPOLARCMOS16BITBUSTRANSCEIVERWITHTHREESTATEOUTPUTSMONOLITHICSILICONPDF

链接地址:http://www.mydoc123.com/p-689221.html