DLA DSCC-VID-V62 04737 REV A-2011 MICROCIRCUIT DIGITAL OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS MONOLITHIC SILICON.pdf
《DLA DSCC-VID-V62 04737 REV A-2011 MICROCIRCUIT DIGITAL OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS MONOLITHIC SILICON.pdf》由会员分享,可在线阅读,更多相关《DLA DSCC-VID-V62 04737 REV A-2011 MICROCIRCUIT DIGITAL OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS MONOLITHIC SILICON.pdf(10页珍藏版)》请在麦多课文档分享上搜索。
1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Update boilerplate paragraphs to current requirements. - PHN 11-09-16 Thomas M. Hess CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing RE
2、V PAGE REV PAGE REV STATUS OF PAGES REV A A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 10 PMIC N/A PREPARED BY Phu H. Nguyen DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL, OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
3、, MONOLITHIC SILICON YY MM DD 04-07-08 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/04737 REV A PAGE 1 OF 10 AMSC N/A 5962-V078-11 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO S
4、IZE A CODE IDENT NO. 16236 DWG NO. V62/04737 REV A PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance octal bus transceiver with 3-state outputs microcircuit, with an operating temperature range of -40C to +85C. 1.2 Vendor Item Drawing Administrative Con
5、trol Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/04737 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3)
6、 1.2.1 Device type(s). Device type Generic Circuit function 01 SN74LVC245A-EP Octal bus transceiver with 3-state outputs. 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 20 JEDEC MO-153 Plastic small outline package 1.2.3 L
7、ead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other 1.3 Absolute maximum ratings. 1/ Supply voltage range, (VCC) . -0
8、.5 V to +6.5 V Input voltage range, (VI) . -0.5 V to +6.5 V 2/ Voltage range applied to any output in the high impedance or power-off stage, (VO) -0.5 V to +6.5 V 2/ Voltage range applied to any output in the high or slow state, (VO) . -0.5 V to VCC+ 0.5 V 2/ 3/ Input clamp current, (IIK) (VI 0) -50
9、 mA Output clamp current, (IOK) (VO 0) . -50 mA Continuous output current, (IO) . 50 mA Continuous current through VCCor GND 100 mA Package thermal impedance (JA) 83C/W 4/ Storage temperature range, (TSTG) -65C to +150C 1/ Stresses beyond those listed under “absolute maximum rating” may cause perman
10、ent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliab
11、ility. 2/ The input and output negative voltage ratings may exceeded if the input and output current ratings are observed. 3/ The value of VCCis provided in the recommended operating conditions table. 4/ The package thermal impedance is calculated in accordance with JESD 51-7. Provided by IHSNot for
12、 ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04737 REV A PAGE 3 1.4 Recommended operating conditions. 5/ TA= 25C -40C to +85C Unit Min Max Min Max Supply voltage, (VCC) Operating 1.6
13、5 3.6 1.65 3.6 V Data retention only 1.5 1.5 High level input voltage, (VIH) VCC= 1.65 V to 1.95 V 0.65 x VCC0.65 x VCCVCC= 2.3 V to 2.7 V 1.7 1.7 VCC= 2.7 V to 3.6 V 2 2 Low level input voltage, (VIL) VCC= 1.65 V to 1.95 V 0.35 x VCC0.35 x VCCVCC= 2.3 V to 2.7 V 0.7 0.7 VCC= 2.7 V to 3.6 V 0.8 0.8
14、Input voltage, (VI) 0 5.5 0 5.5 Output voltage, (VO) 0 VCC0 VCCHigh level output current, (IOH) VCC= 1.65 -4 -4 mA VCC= 2.3 V -8 -8 VCC= 2.7 V -12 -12 VCC= 3 V -24 -24 Low level output current, (IOL) VCC= 1.65 4 4 VCC= 2.3 V 8 8 VCC= 2.7 V 12 12 VCC= 3 V 24 24 Input transition rise or fall rate, (t/
15、v) 10 10 ns/V 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Stre
16、et, Suite 240S, Arlington, VA 22201.) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit containe
17、r. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 5/ All unused inputs of the device must be held at VCCor GND to ensure proper device operation. Provided by IHSNot for ResaleNo reproduction or networking permitted without license
18、from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04737 REV A PAGE 4 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Des
19、ign, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline(s). The case outline(s) shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2.
20、3.5.3 Logic diagram. The logic diagram shall be as shown in figure 3. 3.5.4 Function table. The function table shall be as shown in figure 4. 3.5.5 Load circuit and voltage waveforms. The load circuit and timing waveforms shall be as specified in figure 5. Provided by IHSNot for ResaleNo reproductio
21、n or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04737 REV A PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions unless otherwise specified VCCTA= 25C -40C to +85C Unit Min Max
- 1.请仔细阅读文档,确保文档完整性,对于不预览、不比对内容而直接下载带来的问题本站不予受理。
- 2.下载的文档,不会出现我们的网址水印。
- 3、该文档所得收入(下载+内容+预览)归上传者、原创作者;如果您是本文档原作者,请点此认领!既往收益都归您。
下载文档到电脑,查找使用更方便
10000 积分 0人已下载
下载 | 加入VIP,交流精品资源 |
- 配套讲稿:
如PPT文件的首页显示word图标,表示该PPT已包含配套word讲稿。双击word图标可打开word文档。
- 特殊限制:
部分文档作品中含有的国旗、国徽等图片,仅作为作品整体效果示例展示,禁止商用。设计者仅对作品中独创性部分享有著作权。
- 关 键 词:
- DLADSCCVIDV6204737REVA2011MICROCIRCUITDIGITALOCTALBUSTRANSCEIVERWITH3STATEOUTPUTSMONOLITHICSILICONPDF
链接地址:http://www.mydoc123.com/p-689184.html