DLA DSCC-VID-V62 04657 REV A-2008 MICROCIRCUIT DIGITAL LOW VOLTAGE CMOS 3-LINE TO 8-LINE DECODER DEMULTIPLEXER MONOLITHIC SILICON.pdf
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1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Add device type 02. - phn 08-11-19 Thomas M. Hess Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV A A A A A A A A A A A REV STATUS OF PAGES PAGE 1 2 3 4 5 6 7 8 9 10 11 PMIC N/A PREPARED BY Charles F. Saffle DEFENSE SUPPLY
2、CENTER, COLUMBUS COLUMBUS, OHIO Original date of drawing CHECKED BY Charles F. Saffle APPROVED BY Thomas M. Hess TITLE MICROCIRCUIT, DIGITAL, LOW VOLTAGE CMOS, 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER, MONOLITHIC SILICON SIZE A CODE IDENT. NO. 16236 DWG NO. V62/04657 YY-MM-DD 04-03-08 REV A PAGE 1 OF
3、11 AMSC N/A 5962-V005-09 .Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04657 REV A PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of
4、 a high performance 3-line to 8-line decoder/demultiplexer microcircuit, with an operating temperature range of -40C to +125C (device type 01) and an extend operating temperature range of -55C to +125C (device type 02). 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is
5、the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/04657 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Gen
6、eric Circuit function 01 1/ SN74LVC138A-EP 3-line to 8-line decoder/demultiplexer 02 2/ SN74LVC138A-EP 3-line to 8-line decoder/demultiplexer 1.2.2 Case outlines. The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 16 MS-012 Plastic small-outline Y M
7、O-153 Plastic small-outline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium _ 1/ Device type 01 operated at -40C to
8、 +125C 2/ Device type 02 operated at -55C to +125C Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04657 REV A PAGE 3 1.3 Absolute maximum ratings. 3/ Supply volta
9、ge range (VCC) . -0.5 V to 6.5 V Input voltage range (VI). -0.5 V to 6.5 V 4/ Output voltage range (VO) . -0.5 V to VCC+ 0.5 V 4/ 5/ Input clamp current (IIK) (VI 0) -50 mA Output clamp current (IOK) (VO 0) . -50 mA Continuous output current (IO). 50 mA Continuous current through VCCor GND. 100 mA P
10、ackage thermal impedance (JA): 6/ X package . 73C/W Y package . 108C/W Storage temperature range (TSTG). -65C to 150C 7/ 1.4 Recommended operating conditions. 8/ Supply voltage range (VCC): Operating. 2.0 V to 3.6 V Data retention only 1.5 V minimum Minimum high level input voltage (VIH) (VCC= 2.7 V
11、 to 3.6 V) . 2.0 V Maximum low level input voltage (VIL) (VCC= 2.7 V to 3.6 V) 0.8 V Input voltage range (VI). 0.0 V to 5.5 V Output voltage range (VO) . 0.0 V to VCCMaximum high level output current (IOH): VCC= 2.7 V -12 mA VCC= 3.0 V -24 mA Maximum low level output current (IOL): VCC= 2.7 V 12 mA
12、VCC= 3.0 V 24 mA Maximum input transition rise or fall rate (t/v) . 10 ns/V Operating free-air temperature range (TA): Device type 01 -40C to +125C Device type 02 -55C to +125C 3/ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress
13、 ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 4/ The input negative-voltage and o
14、utput voltage ratings may be exceeded if the input and output current ratings are observed. 5/ The value of VCCis provided in the recommended operating conditions table. 6/ The package thermal impedance is calculated in accordance with JESD 51-7. 7/ Long-term high-temperature storage and/or extended
15、 use at maximum recommended operating conditions may result in a reduction of overall device life. 8/ All unused inputs of the device must be held at VCCor GND to ensure proper device operation. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE
16、 SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04657 REV A PAGE 4 2. APPLICABLE DOCUMENTS JEDEC PUB 95 - Registered and Standard Outlines for Semiconductor Devices JEDEC STD 51-7 - High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Appl
17、ications for copies should be addressed to the Electronic Industry Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows:
18、 A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operati
19、ng conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outlines. The case outlines shall be as sho
20、wn in 1.2.2 and figure 1. 3.5.2 Truth table. The truth table shall be as shown in figure 2. 3.5.3 Logic diagram. The logic diagram shall be as shown in figure 3. 3.5.4 Terminal connections. The terminal connections shall be as shown in figure 4. 3.5.5 Test circuit and timing waveforms. The test circ
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