DLA DSCC-VID-V62 04656 REV B-2012 MICROCIRCUIT DIGITAL LOW VOLTAGE CMOS QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS MONOLITHIC SILICON.pdf
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1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Add device type 02. Add case outline Y. Update boilerplate to current revision. - CFS 06-12-15 Thomas M. Hess B Update boilerplate paragraphs to current requirements. - PHN 12-07-23 Thomas M. Hess CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO
2、: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV B B B B B B B B B B B PAGE 1 2 3 4 5 6 7 8 9 10 11 PMIC N/A PREPARED BY Charles F. Saffle DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990
3、Original date of drawing CHECKED BY Charles F. Saffle TITLE MICROCIRCUIT, DIGITAL, LOW VOLTAGE CMOS, QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS, MONOLITHIC SILICON YY-MM-DD 04-02-24 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/04656 REV B PAGE 1 OF 11 AMSC N/A 5962-V086-12
4、 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04656 REV B PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance quadr
5、uple bus buffer gate with 3-state outputs microcircuit, with an operating temperature range of -40C to +85C for device 01 and an operating temperature range of -55C to +125C for device 02. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The
6、 vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/04656 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 SN74LV
7、C125A-EP Quadruple bus buffer gate with 3-state outputs 02 SN74LVC125A-EP Quadruple bus buffer gate with 3-state outputs 1.2.2 Case outlines. The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 14 MO-153 Plastic small-outline Y 14 MS-012 Plastic smal
8、l-outline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or
9、networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04656 REV B PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) . -0.5 V to 6.5 V Input voltage range (VI) . -0.5 V to 6.5 V 2/ Output voltage range
10、 (VO) . -0.5 V to VCC+ 0.5 V 2/ 3/ Input clamp current (IIK) (VI 0) -50 mA Output clamp current (IOK) (VO 0) . -50 mA Continuous output current (IO) . 50 mA Continuous current through VCCor GND . 100 mA Package thermal impedance (JA): 4/ Case outline X . 113C/W Case outline Y . 86.2C/W Storage tempe
11、rature range (TSTG) . -65C to 150C 1.4 Recommended operating conditions. 5/ Supply voltage range (VCC): Operating 1.65 V to 3.6 V Data retention only 1.5 V minimum Minimum high level input voltage (VIH): (VCC= 1.65 V to 1.95 V) 0.65 x VCC(VCC= 2.3 V to 2.7 V) 1.7 V (VCC= 2.7 V to 3.6 V) 2.0 V Maximu
12、m low level input voltage (VIL): (VCC= 1.65 V to 1.95 V) 0.35 x VCC(VCC= 2.3 V to 2.7 V) 0.7 V (VCC= 2.7 V to 3.6 V) 0.8 V Input voltage range (VI) . 0.0 V to 5.5 V Output voltage range (VO) . 0.0 V to VCCMaximum high level output current (IOH): VCC= 1.65 V -4 mA VCC= 2.3 V -8 mA VCC= 2.7 V -12 mA V
13、CC= 3.0 V -24 mA Maximum low level output current (IOL): VCC= 1.65 V 4 mA VCC= 2.3 V 8 mA VCC= 2.7 V 12 mA VCC= 3.0 V 24 mA Maximum input transition rise or fall rate (t/v) . 8 ns/V Operating free-air temperature range (TA): Case outline X . -40C to +85C Case outline Y . -55C to +125C 1/ Stresses be
14、yond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-max
15、imum-rated conditions for extended periods may affect device reliability. 2/ The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 3/ The value of VCCis provided in the recommended operating conditions table. 4/ The package therma
16、l impedance is calculated in accordance with JESD 51-7. 5/ All unused inputs of the device must be held at VCCor GND to ensure proper device operation. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZ
17、E A CODE IDENT NO. 16236 DWG NO. V62/04656 REV B PAGE 4 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEP95 Registered and Standard Outlines for Semiconductor Devices JESD51-7 High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Copies of these
18、 documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201.) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and
19、as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommen
20、ded operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outlines. The case outlines shal
21、l be as shown in 1.2.2 and figure 1. 3.5.2 Truth table. The truth table shall be as shown in figure 2. 3.5.3 Logic diagram. The logic diagram shall be as shown in figure 3. 3.5.4 Terminal connections. The terminal connections shall be as shown in figure 4. 3.5.5 Test circuit and timing waveforms. Th
22、e test circuit and timing waveforms shall be as shown in figure 5. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04656 REV B PAGE 5 TABLE I. Electrical performan
23、ce characteristics. 1/ Test Symbol Conditions VCCTemperature, TADevice type Limits Unit Min Max High level output voltage VOHIOH= -100 A 1.65 V to 3.6 V Device 01: 25C, -40C to 85C, Device 02: 25C, -55C to 125C 01, 02 VCC 0.2 V IOH= -4 mA 1.65 V 1.2 IOH= -8 mA 2.3 V 1.7 IOH= -12 mA 2.7 V 2.2 3.0 V 2
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