DLA DSCC-VID-V62 04618 REV A-2010 MICROCIRCUIT DIGITAL-LINEAR LOW VOLTAGE 10-BIT ANALOG TO DIGITAL CONVERTER WITH SERIAL CONTROL AND 8 ANALOG INPUTS MONOLITHIC SILICON.pdf
《DLA DSCC-VID-V62 04618 REV A-2010 MICROCIRCUIT DIGITAL-LINEAR LOW VOLTAGE 10-BIT ANALOG TO DIGITAL CONVERTER WITH SERIAL CONTROL AND 8 ANALOG INPUTS MONOLITHIC SILICON.pdf》由会员分享,可在线阅读,更多相关《DLA DSCC-VID-V62 04618 REV A-2010 MICROCIRCUIT DIGITAL-LINEAR LOW VOLTAGE 10-BIT ANALOG TO DIGITAL CONVERTER WITH SERIAL CONTROL AND 8 ANALOG INPUTS MONOLITHIC SILICON.pdf(23页珍藏版)》请在麦多课文档分享上搜索。
1、 REVISIONSLTR DESCRIPTION DATE APPROVEDA Update boilerplate paragraphs to current requirements. - ro 10-11-08 C. SAFFLE CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE R
2、EV A A A A A A PAGE 18 19 20 21 22 23 REV STATUS OF PAGES REV A A A A A A A A A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PMIC N/A PREPARED BY RICK OFFICER DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing YY-MM-DD CHECKED BY TOM HESS TITLE MICROC
3、IRCUIT, DIGITAL-LINEAR, LOW VOLTAGE 10-BIT ANALOG TO DIGITAL CONVERTER WITH SERIAL CONTROL AND 8 ANALOG INPUTS, MONOLITHIC SILICON 03-11-14 APPROVED BY RAYMOND MONNIN SIZE A CODE IDENT. NO. 16236 DWG NO. V62/04618 REV A PAGE 1 OF 23 AMSC N/A 5962-V073-10 Provided by IHSNot for ResaleNo reproduction
4、or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04618 REV A PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance low voltage 10-bit analog to digital converter with
5、serial control and 8 analog inputs microcircuit, with an operating temperature range of -40C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the
6、item on the engineering documentation: V62/04618 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 TLV1548 Low voltage 10 bit analog to digital converter with serial control and 8 analog inpu
7、ts 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 20 MO-150 Plastic small outline1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture: Finish designat
8、or Material A Hot solder dip B Tin-lead plateC Gold plateD PalladiumE Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04618 REV A PAGE
9、3 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) -0.5 V dc to +6.5 V dc 2/ Input voltage range (VI) (any input) . -0.3 V to VCC+0.3 V Output voltage range (VO) . -0.3 V to VCC+0.3 V Positive reference voltage, ( Vref +) . VCC+ 0.1 V Negative reference voltage, ( Vref - ) -0.1 V Peak inp
10、ut current II(any input) 20 mA Peak total input current (all inputs) . -30 mA Storage temperature range (TSTG) -65C to +150C Lead temperature 1, 6 mm (1/16 inch) from case for 10 seconds +260C Thermal resistance, junction-to-air (JA) 114.2C/W 1.4 Recommended operating conditions. 3/ Supply voltage r
11、ange (VCC) +2.7 V dc to +5.5 V dc Positive reference voltage, ( Vref+) VCC nominal 4/ Negative reference voltage, ( Vref-) . 0 V nominal4/ Differential reference voltage, ( Vref+-Vref-) +2.5 V dc to VCC + 0.2 V dc 4/ Analog input voltage range (VI) 0 to VCC4/ High level control input voltage, (VIH)
12、. 2.1 V dc minimum Low level control input voltage, (VIL) 0.6 V dc maximum Setup time, input data bits valid before I/O CLK, tsu (A) . 100 ns minimum Hold time, input data bits valid after I/O CLK, th(A) 5 ns minimum Setup time, CS to I/O CLK, tsu(CS) . 5 ns minimum 5/ Hold time, I/O CLK to CS , th(
13、CS) 65 ns minimum Pulse duration, FS high, twH(FS) 1 I/O CLK periods minimum 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those i
14、ndicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ All voltage values are with respect to GND with REF- and GND wired together (unless otherwise noted). 3/ Use of this product beyond t
15、he manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. 4/ Analog input voltages greater than that applied to REF+ convert as all ones (1111111111), while inpu
16、t voltage less than that applied to REF- convert as all zeros (0000000000). The device is functional with reference voltages down to 1 V (Vref +- Vref -); however, the electrical specifications are no longer applicable. 5/ To minimize errors caused by noise as CS the internal circuitry waits for a s
17、etup time after CS before responding to control input signals. No attempt should be made to clock in an input data until the minimum CS setup time has elapsed. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, O
18、HIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04618 REV A PAGE 4 1.4 Recommended operating conditions - continued. 3/ Pulse duration, CSTART , tw(CSTART) source impedance 1 k, VCC= 5.5 V . 0.84 s minimum Setup time, CS to CSTART , tsu(CSTART) 10 ns minimum Clock frequency at I/O CLK , fCLK; VCC= 5.5 V
19、 . 0.1 to 10 MHz VCC= 2.7 V . 0.1 to 2.81 MHz Pulse duration, I/O CLK high, twH(I/O); VCC= 5.5 V 50 ns minimum VCC= 2.7 V . 100 ns minimum Pulse duration, I/O CLK low, twL(I/O); VCC= 5.5 V . 50 ns minimum VCC= 2.7 V . 100 ns minimum Junction temperature (TJ) . 150C Operating free-air temperature ran
20、ge (TA) . -40C to +125C 2. APPLICABLE DOCUMENTS JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 3. REQUIREMENT
21、S 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manuf
22、acturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The desig
23、n, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Truth table. The truth table shall be as shown in fi
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