DLA DSCC-VID-V62 04617 REV A-2010 MICROCIRCUIT DIGITAL ADVANCED CMOS DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET MONOLITHIC SILICON.pdf

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1、 REVISIONSLTR DESCRIPTION DATE APPROVEDA Update boilerplate paragraphs to current requirements. - PHN 10-02-10 Thomas M. Hess Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 PMIC N/A PREPARED BY Charles F. Saffle DEFE

2、NSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing CHECKED BY Charles F. Saffle TITLE MICROCIRCUIT, DIGITAL, ADVANCED CMOS, DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET, MONOLITHIC SILICON YY-MM-DD 03-11-13 APPROVED BY Thomas M. Hess SIZE A CODE IDE

3、NT. NO. 16236 DWG NO. V62/04617 REV A PAGE 1 OF 11 AMSC N/A 5962-V029-10 .Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04617 REV A PAGE 2 1. SCOPE 1.1 Scope. Th

4、is drawing documents the general requirements of a high performance dual positive-edge-triggered D-type flip-flop with clear and preset microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of iden

5、tification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/04617 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit fun

6、ction 01 74AC74-EP Dual positive-edge-triggered D-type flip-flop with clear and preset 1.2.2 Case outlines. The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 14 JEDEC MS-012 Plastic small-outline 1.2.3 Lead finishes. The lead finishes are as specif

7、ied below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plateC Gold plateD PalladiumE Gold flash palladium Z Other 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) . -0.5 V to +7.0 V Input voltage range (VI) . -0.5 V

8、to VCC+ 0.5 V 2/ Output voltage range (VO) . -0.5 V to VCC+ 0.5 V 2/ Input clamp current (IIK) (VIVCC) 20 mA Output clamp current (IOK) (VOVCC) 20 mA Continuous output current (IO) (VO= 0 to VCC) 50 mA Continuous current through VCCor GND . 200 mA Package thermal impedance (JA) . 86C/W 3/ Storage te

9、mperature range (TSTG) . -65C to +150C 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating

10、conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 3/ The package thermal impedance is calculated in accordance wit

11、h JESD 51-7. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04617 REV A PAGE 3 1.4 Recommended operating conditions. 4/ 5/ Supply voltage range (VCC) . 2.0 V to 6

12、.0 V Minimum high level input voltage (VIH): VCC= 3.0 V 2.1 V VCC= 4.5 V 3.15 V VCC= 5.5 V 3.85 V Maximum low level input voltage (VIL): VCC= 3.0 V 0.9 V VCC= 4.5 V 1.35 V VCC= 5.5 V 1.65 V Input voltage range (VI) . 0.0 V to VCCOutput voltage range (VO) . 0.0 V to VCCMaximum high level output curre

13、nt (IOH): VCC= 3.0 V -12 mA VCC= 4.5 V -24 mA VCC= 5.5 V -24 mA Maximum low level output current (IOL): VCC= 3.0 V 12 mA VCC= 4.5 V 24 mA VCC= 5.5 V 24 mA Maximum input transition rise or fall rate (t/v) . 8 ns/V Operating free-air temperature range (TA) -55C to +125C 2. APPLICABLE DOCUMENTS JEDEC P

14、UB 95 - Registered and Standard Outlines for Semiconductor Devices JESD 51-7 - High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or onlin

15、e at http:/www.jedec.org) 4/ All unused inputs of the device must be held at VCCor GND to ensure proper device operation. 5/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or lia

16、bility for product used beyond the stated limits. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04617 REV A PAGE 4 3. REQUIREMENTS 3.1 Marking. Parts shall be pe

17、rmanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with it

18、ems A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical di

19、mensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Truth table. The truth table shall be as shown in figure 2. 3.5.3 Logic diagram. The logic diagram shall be as shown in figure 3. 3.5.4 Terminal connections. The termin

20、al connections shall be as shown in figure 4. 3.5.5 Timing waveforms and test circuit. The timing waveforms and test circuit shall be as shown in figure 5. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO

21、 SIZE A CODE IDENT NO. 16236 DWG NO. V62/04617 REV A PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions VCCTemperature, TADevice type Limits Unit Min Max High level output voltage VOHIOH= -50 A 3.0 V 25C, -55C to 125C 01 2.9 V 4.5 V 4.4 5.5 V 5.4 IOH= -12 mA 3.0 V 25C

22、2.56 -55C to 125C 2.4 IOH= -24 mA 4.5 V 25C 3.86 -55C to 125C 3.7 5.5 V 25C 4.86 -55C to 125C 4.7 Low level output voltage VOLIOL= 50 A 3.0 V 25C, -55C to 125C 01 0.1 V 4.5 V 0.1 5.5 V 0.1 IOL= 12 mA 3.0 V 25C 0.36 -55C to 125C 0.5 IOL= 24 mA 4.5 V 25C 0.36 -55C to 125C 0.5 5.5 V 25C 0.36 -55C to 12

23、5C 0.5 Input current IIData pins and Control pins VI= VCCor GND 5.5 V 25C 01 0.1 A -55C to 125C 1.0 Quiescent supply current ICCVI= VCCor GND IO= 0 A 5.5 V 25C 01 2.0 A -55C to 125C 40.0 Input capacitance CIVI= VCCor GND 5.0 V 25C 01 3 TYP pF Power dissipation capacitance CpdCL= 50 pF f = 1 MHz 3.3

24、V 25C 01 45 TYP pF Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04617 REV A PAGE 6 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol C

25、onditions VCCTemperature, TADevice type Limits Unit Min Max Clock frequency fclockSee figure 5 3.0 V and 3.6 V 25C 01 100 MHz -55C to 125C 70 4.5 V and 5.5 V 25C 140 -55C to 125C 95 Pulse duration twPRE or CLR low See figure 5 3.0 V and 3.6 V 25C 01 5.5 ns -55C to 125C 8.0 4.5 V and 5.5 V 25C 4.5 -5

26、5C to 125C 5.5 CLK See figure 5 3.0 V and 3.6 V 25C 5.5 -55C to 125C 8.0 4.5 V and 5.5 V 25C 4.5 -55C to 125C 5.5 Setup time, data before CLK tsuData See figure 5 3.0 V and 3.6 V 25C 01 4.0 ns -55C to 125C 5.0 4.5 V and 5.5 V 25C 3.0 -55C to 125C 4.0 PRE or CLR inactive See figure 5 3.0 V and 3.6 V

27、25C 0.0 -55C to 125C 0.5 4.5 V and 5.5 V 25C 0.0 -55C to 125C 0.5 Hold time, data after CLK thSee figure 5 3.0 V and 3.6 V 25C 01 0.5 ns -55C to 125C 0.5 4.5 V and 5.5 V 25C 0.5 -55C to 125C 0.5 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE

28、 SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04617 REV A PAGE 7 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Conditions VCCTemperature, TADevice type Limits Unit Min Max Maximum clock frequency fmaxSee figure 5 3.0 V and 3.6 V 25C 01

29、100 MHz -55C to 125C 70 4.5 V and 5.5 V 25C 140 -55C to 125C 95 Propagation delay time, PRE or CLR to Q or Q tPLHSee figure 5 3.0 V and 3.6 V 25C 01 3.5 12.0 ns -55C to 125C 1.0 13.0 4.5 V and 5.5 V 25C 2.5 9.0 -55C to 125C 1.0 9.5 tPHLSee figure 5 3.0 V and 3.6 V 25C 4.0 12.0 -55C to 125C 1.0 14.0

30、4.5 V and 5.5 V 25C 3.0 9.5 -55C to 125C 1.0 10.5 Propagation delay time, CLK to Q or Q tPLHSee figure 5 3.0 V and 3.6 V 25C 01 4.5 13.5 ns -55C to 125C 1.0 17.5 4.5 V and 5.5 V 25C 3.5 10.0 -55C to 125C 1.0 12.0 tPHLSee figure 5 3.0 V and 3.6 V 25C 3.5 14.0 -55C to 125C 1.0 13.5 4.5 V and 5.5 V 25C

31、 2.5 10.0 -55C to 125C 1.0 10.0 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily b

32、e tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG

33、NO. V62/04617 REV A PAGE 8 Case X Dimensions Symbol Millimeters Inches Symbol Millimeters Inches Min Max Min Max Min Max Min Max A - 1.75 - .069 E 3.81 4.00 .150 .157 A1 0.10 0.25 .004 .010 E1 5.80 6.20 .228 .244 b 0.35 0.51 .014 .020 e 1.27 NOM .050 NOM c 0.20 NOM .008 NOM L 0.40 1.12 .016 .044 D 8

34、.55 8.75 .337 .344 NOTES: 1. This drawing is subject to change without notice. 2. Body dimensions do not include mold flash or protrusion not to exceed 0.006 inches (0.15 mm). 3. Falls within JEDEC MS-012. 4. All linear dimensions are shown in inches (millimeters). Metric equivalents are given for g

35、eneral information only. FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04617 REV A PAGE 9 Inputs Outputs PRE CLR CLK D Q Q L H X X H L H

36、L X X L H L L X X H* H* H H H H L H H L L H H H L X Q0QonullnullnullnullX = Immaterial = Rising edge of CLK * = This configuration is nonstable; that is, it does not persist when either PRE or CLR returns to its inactive (high) level. FIGURE 2. Truth table. FIGURE 3. Logic diagram. Device type 01 Ca

37、se outlines: X and Y Terminal number Terminal symbol Terminal number Terminal symbol 1 1CLRnullnullnullnullnull8 2Qnull2 1D 9 2Q 3 1CLK 10 1PREnullnullnullnullnullnull4 1PREnullnullnullnullnullnull11 2CLK 5 1Q 12 2D6 1Qnull13 1PREnullnullnullnullnullnull7 GND 14 VCCFIGURE 4. Terminal connections. Pr

38、ovided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04617 REV A PAGE 10 NOTES: 1. CLincludes probe and jig capacitance. 2. All input pulses are supplied by generators ha

39、ving the following characteristics: PRR 1 MHz, ZO= 50, tr 2.5 ns, tf 2.5 ns. 3. The outputs are measured one at a time with one input transition per measurement. 4. For tPLH/tPHLtests, S1 = Open FIGURE 5. Timing waveforms and test circuit. Provided by IHSNot for ResaleNo reproduction or networking p

40、ermitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04617 REV A PAGE 11 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in the

41、ir internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in ac

42、cordance with the manufacturers standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient chara

43、cteristics of the device manufacturers data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as

44、a guarantee of present or continued availability as a source of supply for the item. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Vendor part number Top-Side Marking V62/04617-01XE 01295 SN74AC74MDREP SAC74MEP 1/ The vendor item drawing establishes an administra

45、tive control number for identifying the item on the engineering documentation. CAGE code Source of supply 01295 Texas Instruments, Inc. Semiconductor Group8505 Forest lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-