DLA DSCC-VID-V62 04616 REV A-2010 MICROCIRCUIT DIGITAL ADVANCED CMOS QUADRUPLE 2-INPUT POSITIVE OR GATE MONOLITHIC SILICON.pdf
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1、 REVISIONSLTR DESCRIPTION DATE APPROVEDA Update boilerplate paragraphs to current requirements. - PHN 10-02-10 Thomas M. Hess Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV A A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 10 PMIC N/A PREPARED BY Charl
2、es F. Saffle DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing CHECKED BY Charles F. Saffle TITLE MICROCIRCUIT, DIGITAL, ADVANCED CMOS, QUADRUPLE 2-INPUT POSITIVE OR GATE, MONOLITHIC SILICON YY-MM-DD 03-11-13 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DW
3、G NO. V62/04616 REV A PAGE 1 OF 10 AMSC N/A 5962-V028-10 .Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04616 REV A PAGE 2 1. SCOPE 1.1 Scope. This drawing docum
4、ents the general requirements of a high performance quadruple 2-input positive OR gate microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes a
5、n administrative control number for identifying the item on the engineering documentation: V62/04616 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 74AC32-EP Quadruple 2-input positive OR
6、gate 1.2.2 Case outlines. The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 14 JEDEC MS-012 Plastic small-outline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish de
7、signator Material A Hot solder dip B Tin-lead plateC Gold plateD PalladiumE Gold flash palladium Z Other 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) . -0.5 V to +7.0 V Input voltage range (VI) . -0.5 V to VCC+ 0.5 V 2/ Output voltage range (VO) . -0.5 V to VCC+ 0.5 V 2/ Input clamp c
8、urrent (IIK) (VIVCC) 20 mA Output clamp current (IOK) (VOVCC) 20 mA Continuous output current (IO) (VO= 0 to VCC) 50 mA Continuous current through VCCor GND . 200 mA Package thermal impedance (JA) . 86C/W 3/ Storage temperature range (TSTG) . -65C to +150C 1/ Stresses beyond those listed under “abso
9、lute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for exte
10、nded periods may affect device reliability. 2/ The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 3/ The package thermal impedance is calculated in accordance with JESD 51-7. Provided by IHSNot for ResaleNo reproduction or networking permitted
11、without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04616 REV A PAGE 3 1.4 Recommended operating conditions. 4/ 5/ Supply voltage range (VCC) . 2.0 V to 6.0 V Minimum high level input voltage (VIH): VCC= 3.0 V 2.1 V VCC= 4.5 V 3.15 V VC
12、C= 5.5 V 3.85 V Maximum low level input voltage (VIL): VCC= 3.0 V 0.9 V VCC= 4.5 V 1.35 V VCC= 5.5 V 1.65 V Input voltage range (VI) . 0.0 V to VCCOutput voltage range (VO) . 0.0 V to VCCMaximum high level output current (IOH): VCC= 3.0 V -12 mA VCC= 4.5 V -24 mA VCC= 5.5 V -24 mA Maximum low level
13、output current (IOL): VCC= 3.0 V 12 mA VCC= 4.5 V 24 mA VCC= 5.5 V 24 mA Maximum input transition rise or fall rate (t/v) . 8 ns/V Operating free-air temperature range (TA) -55C to +125C 2. APPLICABLE DOCUMENTS JEDEC PUB 95 - Registered and Standard Outlines for Semiconductor Devices JESD 51-7 - Hig
14、h Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently
15、and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and
16、C (if applicable) above. 4/ All unused inputs of the device must be held at VCCor GND to ensure proper device operation. 5/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liab
17、ility for product used beyond the stated limits. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04616 REV A PAGE 4 3.3 Electrical characteristics. The maximum and
18、 recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outli
19、ne shall be as shown in 1.2.2 and figure 1. 3.5.2 Truth table. The truth table shall be as shown in figure 2. 3.5.3 Logic diagram. The logic diagram shall be as shown in figure 3. 3.5.4 Terminal connections. The terminal connections shall be as shown in figure 4. 3.5.5 Timing waveforms and test circ
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