DLA DSCC-VID-V62 04608 REV A-2009 MICROCIRCUIT DIGITAL DSP CONTROLLERS MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Update boilerplate paragraphs to current requirements. - CFS 09-01-27 Charles F. Saffle Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV A A A A A A A A A A A A A A A A A A A A A A PAGE 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33

2、 34 35 36 37 38 39 REV A A A A A A A A A A A A A A A A A REV STATUS OF PAGES PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PMIC N/A PREPARED BY Phu H. Nguyen DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing CHECKED BY Phu H. Nguyen APPROVED BY Thomas M. Hess TITLE

3、MICROCIRCUIT, DIGITAL, DSP CONTROLLERS, MONOLITHIC SILICON SIZE A CODE IDENT. NO. 16236 DWG NO. V62/04608 YY MM DD 04-03-11 REV A PAGE 1 OF 39 AMSC N/A 5962-V024-09 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUM

4、BUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04608 REV A PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance DSP controllers microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. Th

5、e manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/04608 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device t

6、ype(s). 1/ Device type Generic Circuit function 01 SM320LF2407A-EP DSP controllers 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 144 JEDEC MS-026 Plastic Quad flatpack 1.2.3 Lead finishes. The lead finishes are as specifi

7、ed below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other 1.3 Absolute maximum ratings. 2/ Supply voltage range, (DVDD, PLLVCCA, VDDO, and VCCA) . -0.3 V to +4.6 V 3/ VC

8、CP range, . -0.3 V to +5.5 V Input voltage range, (VI) . -0.3 V to +4.6 V Output voltage range, (VO) . -0.3 V to +4.6 V Input clamp current, (IIK) (VINVCC) . 20 mA Output clamp current, (IOK) (VOVCC) . 20 mA Operating case temperature ranges, (TC) M version. -55C to +125C 4/ 5/ Junction temperature

9、range, (TJ) -55C to +130C 5/ Storage temperature range, (TSTG) -65C to +150C 4/ _ 1/ Users are cautioned to review the manufacturers data manual for additional user information relating to this device. 2/ Clamp current stresses beyond those listed under “absolute maximum rating” may cause permanent

10、damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliabilit

11、y. 3/ All voltage values are with respect to VSS. 4/ Long term high temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of overall device life. See manufacturer handout for additional information on enhanced plastic packaging. 5/ See manufact

12、urer handout for device operating life for important information on temperature ranges. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04608 REV A PAGE 3 1.4 Reco

13、mmended operating conditions. 6/ 7/ 8/ Supply voltage, (VDD/VDDO) (VDDO= VDD 0.3 V) +3.0 V to +3.6 V Supply ground, (VSS) 0 V PLL supply voltage, (PLLVCCA) . +3.0 V to +3.6 V ADC supply voltage, (VCCA) +3.0 V to +3.6 V 9/ Flash programming supply voltage, (VCCP) . +4.75 V to +5.25 V Device clock fre

14、quency (system clock), (fCLKOUT) 2 MHz to 40 MHz High level input voltage, (VIH): 10/ XTAL1/CLKIN . +2.2 V to VDD+0.3 V All other inputs +2.0 V to VDD+0.3 V Low level input voltage, (VIL) +0.8 V maximum High level output source current, VOH= 2.4 V (IOH): Output pins group 1 -2 mA maximum 11/ Output

15、pins group 2 -4 mA maximum 11/ Output pins group 3 -8 mA maximum 11/ Low level output current, VOL= VOLMax, (IOL): Output pins group 1 2 mA maximum 11/ Output pins group 2 4 mA maximum 11/ Output pins group 3 8 mA maximum 11/ Operating case temperature (TC) M version . -55C to +125C Junction tempera

16、ture (TJ) . -40C to +130C Flash endurance for the array (Write/erase cycles), (Nf) (-40C to +85C) . 10K Typical cycles Junction to air (RJA) . 44C/W Junction to case (RJC) . 13C/W 10-bit analog to digital converter (ADC) Analog supply voltage, (VCCA) +3.0 V to +3.6 V Analog ground, (VSSA) 0 V Analog

17、 supply reference source, (VREFHI) 12/ . VREFLOto VCCAAnalog ground reference source, (VREFLO) 12/ . VSSAto VREFHIAnalog input voltage, ADCIN00-ADCIN07, (VAI) VREFLOto VREFHI_ 6/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacture

18、r and/or distributor maintain no responsibility or liability for product used beyond the stated limits. 7/ Refer to the mechanical data package page for thermal resistance values, JA(junction to ambient) and JC (junction to case).8/ The drive strength of the EVA PWM pins and the EVB PWM pins are not

19、 identical. 9/ VCCAshould not differ from VDDby more than 0.3 V. 10/ The input buffers used in 240x/240xA are not 5 V compatible. 11/ Primary signals and their groupings: Group 1: PWM1-PWM6, T1PWM, T2PWM, CAP1-CAP6, TCLKINA, IOPC1, TCK, TDI, TMS, XF, A0-A15. Group 2: PS / DS /IS , RD , W/ R , OE_VIS

20、 , D0-D15, T3PWM, T4PWM, PWM7-PWM12, CANTX, CANRX, SPICLK, SPISOMI, SPISIMO, SPISTE , EMU0, EMU1, TDO, TMS2. Group 3: TDIRA, TDIRB, SCIRX, SCITXD, XINT1, XINT2, CLKOUT, TCLKINB. 12/ VREFHIand VREFLOmust be stable, within 1/2 LSB of the required resolution, during the entire conversion time. Provided

21、 by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04608 REV A PAGE 4 2. APPLICABLE DOCUMENTS JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices (Applica

22、tions for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as fo

23、llows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended o

24、perating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline(s). The case outline(s) shall

25、 be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Block diagram. The block diagram shall be as specified in figure 3. 3.5.4 Load circuit. The load circuit shall be as specified in figure 4. 3.5.5 Timing waveforms. The timing

26、 waveforms shall be as shown in figure 5-23. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04608 REV A PAGE 5 TABLE I. Electrical performance characteristics. 1/

27、 Limits Test Symbol Test condition -55C TC+125C 3.0 V VDD/VDDO 3.6 V 4.75 V VCCP 5.25 V unless otherwise noted Min Max Unit SPISOMI 2.2 VDDOVDD= 3.0 V, IOH= IOHMax All other outputs 2.4 VDDOHigh level output voltage VOHAll outputs at 50 A VDDO-0.2 2/ 0.9 Low level output voltage VOLIOL= IOLMax All o

28、ther outputs 0.4 V With pull up -9 -40 Input current (low level) IILVDD= 3.3 V, VIN= 0 V With pull down 2 With pull up 2 Input current (high level) IIHVDD= 3.3 V, VIN= VDDWith pull down 9 40 Output current, high impedance state (off-state) IOZVO= VDDor 0 V 2 A Input capacitance CI2 Typ Output capaci

29、tance CO3 Typ pF Current consumption by power-supply pins at 40 MHz CLOCKOUT Operational current IDD3/ All I/O pins are floating. 4/ 120 ADC module current ICCA20 mA Current consumption by power supply pins during low power modes at 40 MHz CLOCKOUT Operational current IDD3/ 80 Mode: LPM0 5/ ADC modu

30、le current ICCA20 Operational current IDD3/ 45 Mode: LPM1 6/ ADC module current ICCA0 mA Operational current IDD 3/ 400 A Mode: LPM2 7/ 8/ ADC module current ICCA0 mA See notes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE

31、SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04608 REV A PAGE 6 TABLE I. Electrical performance characteristics - Continued. 1/ Limits Test Symbol Test condition -55C TC+125C 3.0 V VDD/VDDO 3.6 V 4.75 V VCCP 5.25 V unless otherwise noted Min Max Unit EXTERNAL REFERE

32、NCE CRYSTAL/CLOCK WITH PLL CIRCUIT ENABLED Timings with the PLL circuit enabled Resonator 4 13 Crystal 4 20 Input clock frequency 9/ fxCLKIN 4 20 MHz Switching characteristics H = 0.5 tc(CO) Cycle time, CLKOUT PLL mode: x4 mode 9/ tc(CO)25 Fall time, CLKOUT tf(CO)4 Typ Rise time, CLKOUT tr(CO)4 Typ

33、Pulse duration, CLKOUT low tW(COL)H-3 H+3 Pulse duration, CLKOUT high tW(COH)H-3 H+3 Transition time, PLL synchronized after RS pin high tt See figure 5 4096tc(CI)ns Timing requirements Cycle time, XTAL1/CLKIN tc(CI)250 Fall time, XTAL1/CLKIN tf(CI)5 Rise time, XTAL1/CLKIN tr(CI)5 ns Pulse duration,

34、 XTAL1/CLKIN low as percentage of tc(CI)tW(CIL)40 60 Pulse duration, XTAL1/CLKIN high as percentage of tc(CI)tW(CIH)See figure 5 40 60 % RS TIMINGS Timing requirements for a reset H = 0.5tc(CO) Pulse duration, stable CLKIN to RS high tW(RSL)8tc(CI)Pulse duration, RS low tW(RSL2) c(CI)cycles PLL lock

35、 up time tp4096tc(CI)Delay time, reset vector executed after PLL lock time td(EX)See figure 6 36H Typ ns Switching characteristics for a reset H = 0.5tc(CO) Pulse duration, RS low 10/ tW(RSL1)128tc(CI)Delay time, reset vector executed after PLL lock time td(EX)36H PLL lock time (input cycles) tpSee

36、figure 7 4096tc(CI)ns See notes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04608 REV A PAGE 7 TABLE I. Electrical performance characteristics

37、 - Continued. 1/ Limits Test Symbol Test condition -55C TC+125C 3.0 V VDD/VDDO 3.6 V 4.75 V VCCP 5.25 V unless otherwise noted Min Max Unit LOW POWER MODE TIMINGS Switching characteristics H = 0.5tc(CO) Low power modes IDLE1 LPM0 12 x tc(CO)Typ Delay time, CLKOUT switching to program execution resum

38、e td(WAKE-A)IDLE2 LPM1 15 x tc(CO)Typ Delay time, Idle instruction executed to CLKOUT high td(IDLE-COH)IDLE2 LPM1 4tc(CO)Typ ns Delay time, wake interrupt asserted to oscillator running td(WAKE-OSC)11/ ms Delay time, idle instruction executed to oscillator power off td(IDLE-OSC)See figure 8 HALT PLL

39、/OSC power down LPM2 4tc(CO)Typ Delay time, reset vector executed after RS high td(EX)36H ns LPM2 WAKEUP TIMINGS Switching characteristics Delay time, PDPINTx low to PWM high impedance state td(PDP-PWM)HZ12 12/ Delay time, INT low/high to interrupt vector fetch td(INT)See figure 9 10tc(CO)ns Timing

40、requirements If bit 6 of SCSR2 = 0 6tc(CO)Pulse duration, PDPINTx input low If bit 6 of SCSR2 = 1 tW(PDP-WAKE)13/ 12tc(CO)PLL lock up time tpSee figure 9 4096tc(CI)ns XF, BIO , AND MP/ MC TIMINGS Switching characteristics Delay time, CLKOUT high to XF high/low td(XF)See figure 10 -7 7 ns Timing requ

41、irements Setup time, BIO or MP/ MC low before CLKOUT low tsu(BIO)CO12 12/ Hold time, BIO or MP/ MC low after CLKOUT low th(BIO)COSee figure 10 22 ns See notes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COL

42、UMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04608 REV A PAGE 8 TABLE I. Electrical performance characteristics - Continued. 1/ Limits Test Symbol Test condition -55C TC+125C 3.0 V VDD/VDDO 3.6 V 4.75 V VCCP 5.25 V unless otherwise noted Min Max Unit TIMING EVENT MANAGER INTERFACE PW

43、M TIMINGS Switching characteristics for PWM timing H = 0.5tc(CO) Pulse duration, PWMx output high/low tW(PWM)14/ 2H-2 Delay time, CLKOUT low to PWMx output switching td(PWM)COSee figure 11 18 ns Timing requirements H = 0.5tc(CO) 15/ Pulse duration, TMRDIR low/high tW(TMRDIR)4H+5 Ns Pulse duration, T

44、MRCLK low as a percentage of TMRCLK cycle time tW(TMRCLK)40 60 Pulse duration, TMRCLK high as a percentage of TMRCLK cycle time tWh(TMRCLK)60 % Cycle time, TMRCLK tc(TMRCLK)See figure 11 4 x tc(CO)ns CAPTURE AND QEP TIMINGS Timing requirements If bit 6 of SCSR2 = 0 6tc(CO)Pulse duration, CAPx input

45、low/high if bit 6 of SCSR2 = 1 tW(CAP)13/ See figure 12 12tc(CO)ns INTERRUPT TIMINGS 16/ Switching characteristics Delay time, PDPINTx low to PWM high impedance state td(PDP-PWM)HZ12 12/ Delay time, INT low/high to interrupt vector fetch td(INT)See figure 13 10tc(CO)ns Timing requirements If bit 6 o

46、f SCSR2 = 0 6tc(CO)Pulse duration, INT input low/high if bit 6 of SCSR2 = 1 tW(INT)13/ 12tc(CO)If bit 6 of SCSR2 = 0 6tc(CO)Pulse duration, PDPINTx input low if bit 6 of SCSR2 = 1 tW(PDP)13/ See figure 13 12tc(CO)ns GENERAL PURPOSE INPUT/OUTPUT TIMINGS Switching characteristics Delay time, CLKOUT lo

47、w to GPIO low/high td(GPIO)CO9 Rise time, GPIO switching low to high tr(GPIO)8 Fall time, GPIO switching high to low tf(GPIO)All GPIOs See figure 14 6 ns Timing requirements H = 0.5tc(CO) Pulse duration, GPI high/low tW(GPI)See figure 14 2H+15 ns See notes at end of table. Provided by IHSNot for Res

48、aleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04608 REV A PAGE 9 TABLE I. Electrical performance characteristics - Continued. 1/ Limits SPI when (SPIBRR +1) is even or SPIBRR = 0 or 2 SPI when (SPIBRR +1) is odd and SPIBRR 3 No. Test Symbol Test condition -5