DLA DSCC-VID-V62 03649 REV A-2009 MICROCIRCUIT DIGITAL ADVANCED HIGH SPEED CMOS OCTAL BUFFER DRIVER WITH 3-STATE OUTPUTS MONOLITHIC SILICON.pdf
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1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Update boilerplate paragraphs to current requirements. - PHN 09-03-16 Thomas M. Hess Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV A A A A A A A A A A A REV STATUS OF PAGES PAGE 1 2 3 4 5 6 7 8 9 10 11 PMIC N/A PREPARED B
2、Y Charles F. Saffle DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing CHECKED BY Charles F. Saffle APPROVED BY Thomas M. Hess TITLE MICROCIRCUIT, DIGITAL, ADVANCED HIGH SPEED CMOS, OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS, MONOLITHIC SILICON SIZE A CODE IDENT. NO. 16
3、236 DWG NO. V62/03649 YY-MM-DD 03-08-13 REV A PAGE 1 OF 11 AMSC N/A 5962-V051-09 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03649 REV A PAGE 2 1. SCOPE 1.1 Sc
4、ope. This drawing documents the general requirements of a high performance octal buffer/driver with 3-state outputs microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vend
5、or item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/03649 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 74AHC244-EP
6、 Octal buffer/driver with 3-state outputs 1.2.2 Case outlines. The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 20 JEDEC MO-153 Plastic small-outline Y 20 JEDEC MS-013 Plastic small-outline 1.2.3 Lead finishes. The lead finishes are as specified b
7、elow or other lead finishes as provided by the device manufacture: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CEN
8、TER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03649 REV A PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) . -0.5 V to +7.0 V Input voltage range (VI). -0.5 V to +7.0 V 2/ Output voltage range (VO) . -0.5 V to VCC+ 0.5 V 2/ Input clamp current (IIK) (VIVCC) 2
9、0 mA Continuous output current (IO) (VO= 0 to VCC) 25 mA Continuous current through VCCor GND. 50 mA Package thermal impedance (JA): X package . 83C/W 3/ Y package . 58C/W 3/ Storage temperature range (TSTG). -65C to +150C 1.4 Recommended operating conditions. 4/ 5/ Supply voltage range (VCC) . 2.0
10、V to 5.5 V Minimum high level input voltage (VIH): VCC= 2.0 V 1.5 V VCC= 3.0 V 2.1 V VCC= 5.5 V 3.85 V Maximum low level input voltage (VIL): VCC= 2.0 V 0.5 V VCC= 3.0 V 0.9 V VCC= 5.5 V 1.65 V Input voltage range (VI). 0.0 V to 5.5 V Output voltage range (VO) . 0.0 V to VCCMaximum high level output
11、 current (IOH): VCC= 2.0 V -50 A VCC= 3.3 V 0.3 V. -4.0 mA VCC= 5.0 V 0.5 V. -8.0 mA Maximum low level output current (IOL): VCC= 2.0 V 50 A VCC= 3.3 V 0.3 V. 4.0 mA VCC= 5.0 V 0.5 V. 8.0 mA Maximum input transition rise or fall rate (t/v): VCC= 3.3 V 0.3 V. 100 ns/V VCC= 5.0 V 0.5 V. 20 ns/V Operat
12、ing free-air temperature range (TA). -55C to +125C 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommende
13、d operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 3/ The package thermal impedance is calculated in ac
14、cordance with JESD 51-7. 4/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. 5/ All unused inputs of the device must be held
15、 at VCCor GND to ensure proper device operation. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03649 REV A PAGE 4 2. APPLICABLE DOCUMENTS JEDEC PUB 95 - Register
16、ed and Standard Outlines for Semiconductor Devices JESD 51-7 - High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.j
17、edec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall
18、be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physi
19、cal dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outlines. The case outlines shall be as shown in 1.2.2 and figure 1. 3.5.2 Truth table. The truth table shall be as shown in figure 2. 3.5.3 Logic diagram. The logic diagram shall be as
20、 shown in figure 3. 3.5.4 Terminal connections. The terminal connections shall be as shown in figure 4. 3.5.5 Timing waveforms and test circuit. The timing waveforms and test circuit shall be as shown in figure 5. Provided by IHSNot for ResaleNo reproduction or networking permitted without license f
21、rom IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03649 REV A PAGE 5 TABLE I. Electrical performance characteristics. 1/ Limits Test Symbol Conditions VCCTemperature TADevice Type Min Max Unit 2.0 V 1.9 3.0 V 2.9 IOH= -50 A 4.5 V 25C, -55C to 125C 4.4
22、 25C 2.58 IOH = -4 mA 3.0 V -55C to 125C 2.48 25C 3.94 High level output voltage VOHIOH= -8 mA 4.5 V -55C to 125C 01 3.80 V 2.0 V 0.1 3.0 V 0.1 IOL= 50 A 4.5 V 25C, -55C to 125C 0.1 25C 0.36 IOL = 4 mA 3.0 V -55C to 125C 0.5 25C 0.36 Low level output voltage VOLIOL= 8 mA 4.5 V -55C to 125C 01 0.5 V
23、25C 0.1 Input current II VI = 5.5 V or GND 0.0 V to 5.5 V -55C to 125C 01 1.0 25C 0.25 3-state output current IOZVO= VCCor GND, VI( OE )= VILor VIH5.5 V -55C to 125C 01 2.5 25C 4.0 Quiescent supply current ICCVI= VCCor GND IO= 0 A 5.5 V -55C to 125C 01 40.0 A Input capacitance CIVI= VCCor GND 5.0 V
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