DLA DSCC-VID-V62 03644 REV A-2009 MICROCIRCUIT LINEAR LOW POWER VOLTAGE REGULATOR MONOLITHIC SILICON.pdf
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1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Make clarification to 1.2.2. Add dimension L and make corrections to the L1 dimensions for both case outlines as specified under figure 1. - ro 09-02-11 R. HEBER Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV A A A A A A A
2、 A A A A A A A REV STATUS OF PAGES PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY RICK OFFICER DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing YY-MM-DD CHECKED BY TOM HESS APPROVED BY RAYMOND MONNIN TITLE MICROCIRCUIT, LINEAR, LOW POWER, VOLTAGE REGULATO
3、R, MONOLITHIC SILICON SIZE A CODE IDENT. NO. 16236 DWG NO. V62/03644 03-08-11 REV A PAGE 1 OF 14 AMSC N/A 5962-V026-09 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO.
4、V62/03644 REV A PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance low power voltage regulator microcircuit, with an operating temperature range of -40C to +85C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of
5、identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/03644 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit
6、 function Voltage 01 TPS79101-EP Low power voltage regulator 1.2 V to 5.5 V 02 TPS79118-EP Low power voltage regulator 1.8 V 03 TPS79133-EP Low power voltage regulator 3.3 V 04 TPS79147-EP Low power voltage regulator 4.7 V 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline l
7、etter Number of pins JEDEC PUB 95 Package style X 5 MO-178-AA Plastic small outline Y 6 MO-178-AB Plastic small outline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture: Finish designator Material A Hot solder dip B Tin-lead p
8、late C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03644 REV A PAGE 3 1.3 Absolute maximum ratings. 1/ In
9、put voltage range -0.3 V to 6 V 2/ Voltage range at EN . -0.3 V to VI+0.3 V Voltage on OUT . -0.3 V to 6 V Peak output current Internally limited ESD rating, HBM 2 kV ESD rating, CDM 500 V Continuous total power dissipation (PD) . See dissipation rating table Operating virtual junction temperature r
10、ange (TJ) -40C to +150C Operating free-air temperature range (TA) . -40C to +85C Storage temperature range (TSTG) -65C to 150C 1.4 Recommended operating conditions. 3/ Input voltage range (VI) 2.7 V to 5.5 V 4/ Continuous output current (IO) . 0 mA to 100 mA 5/ Operating junction temperature (TJ) .
11、-40C to +125C Board Case outlines RJCRJADerating factor above TA= 25C TA 25C Power rating TA= 70C Power rating TA= 85C Power rating Low K 6/ X, Y 63.75C/W 256C/W 3.906 mW/C 391 mW 215 mW 156 mW High K 7/ X, Y 63.75C/W 178.3C/W 5.609 mW/C 561 mW 308 mW 224 mW 1/ Stresses beyond those listed under “ab
12、solute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for ex
13、tended periods may affect device reliability. 2/ All voltage values are with respect to network terminal ground. 3/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability fo
14、r product used beyond the stated limits. 4/ To calculate the minimum input voltage for your maximum output current, use the following formula: VI(min) = VO(max) + VDO(max load). 5/ Continuous output current and operating junction temperature are limited by internal protection circuitry, but it is no
15、t recommended that the device operate under conditions beyond those specified in this table extended periods of time. 6/ The JEDEC low K (1s) board design used to derive this data was a 3-inch x 3-inch, two layer board with 2 ounce copper traces on top of the board. 7/ The JEDEC high K (2s2p) board
16、design used to derive this data was a 3-inch x 3-inch, multi-layer board with 1 ounce internal power and ground planes and 2 ounce copper traces on top and bottom of the board. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, CO
17、LUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03644 REV A PAGE 4 2. APPLICABLE DOCUMENTS JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22
18、201-3834 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit con
19、tainer. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.
20、4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outlines. The case outlines shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2.
21、 3.5.3 Logic diagram. The logic diagram shall be as shown in figure 3. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03644 REV A PAGE 5 TABLE I. Electrical perfo
22、rmance characteristics. Limits Test Symbol Conditions 1/ 2/Temperature, TADevice type Min Max Unit Output voltage VO1.22 V VO 5.2 V TJ= 25C 01 VOtypical V 0 A IO 100 mA, 3/ 1.22 V VO 5.2 V -40C to +85C 0.98VO1.02VOTJ= 25C 02 1.8 typical 0 A IO 100 mA, 2.8 V VI 5.5 V -40C to +85C 1.764 1.836 TJ= 25C
23、03 3.3 typical 0 A IO 100 mA, 4.3 V VI 5.5 V -40C to +85C 3.234 3.366 TJ= 25C 04 4.7 typical 0 A IO 100 mA, 5.2 V VI 5.5 V -40C to +85C 4.606 4.794 IQ0 A IO 100 mA TJ= 25C 01,02, 170 typical A Quiescent current (GND current) -40C to +85C 03,04 250 Load regulation RLD0 A IO 100 mA TJ= 25C 01,02,03,04
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