CEPT T CD 02-02 E-1986 Specification of Engineering Requirements for a Synchronous Digital Multiplexer Operating at 64 KBit s Using a 10 Bit (8+2) Envelope Structure《使用10 Bit(8+2)封.pdf

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1、 02-02 Page E 1 Recommendation T/CD 02-02 E (Ostende 1979, revised at Cannes 1983) concerning the Specification of engineering requirements for a synchronous digital multiplexer operating at 64 kbit/s using a IO-bit (8+2) envelope structure Recommendation proposed by Working Group T/WG 10 “Data Comm

2、unications” (CD) Text of the revised Recommendation adopted by the “Telecornmunicatioris Commission : a .- i- - I u M O .d - 2- 32 62 5 v 0 G id 3 i- 24 o - - 8 5 .5 2 (T/CD 02-02). Functional structure and interfaces of 64 kbit/s data multiplexor system. Edition of March 15, 1986 CEPT T/CD*OZ-OZ*E

3、79 m 232b4LLi 0003495 L m Interchange circuit designation G TT TR TST TSR TLC TA T/CD 02-02 E Page 5 Interchange circuit name Signal ground or common return Tributary channel transmitted data Tributary channel received data Tributary channel transmitter signal element timing (optional) 1) Tributary

4、channel receiver signal element timing (optional) 1) Loop No. 5 control (optional) Received line signal level detector (optional) Dire from mux. Table 2 (T/CD 02-02). Interchange circuits at the internal tributary interface. Notes: 1) In those implementations where a centralized timing source suppli

5、es both, the multiplex equipment and the Tributary interface conversion units external to the multiplex equipment, there are no timing interchange circuits at this interface. In this case the receive tributary channel bufers are situated in the external Tributary interface conversion units. 2) The s

6、peed on this interface is equal to the gross bit rate, the data being organized in 10-bit envelopes. 3) The electrical characteristics of this interface are under study. 4) The definitions of the interchange circuits are under study. 3.2. 64 kbitls interfaces 3.2.1. Extemal 64 Ibitfs intelface Three

7、 main variants of this interface exist. i) A digital interface for direct connection to codirectional or contradirectional interfaces, as defined for access to PCM equipment in CCITT Recommendations G.703 and G.732 paragraphs 5.1. and 5.2. ii) A digital modem interface according to CCITT Recommendat

8、ion X.27 (V. I i). iii) An analogue line interface as defined by the Multiplexed interface conversion unit, cf. Figure 2 The Multiplexed interface conversion unit of the multiplexor, corresponding to variants i) and ii) above would be PCM or modem adaptors. In variant iii) the Multiplexed interface

9、conversion unit would be either a 64 kbit/s baseband transmission equipment or a groupband modem, both designed to be integrated parts of the data multiplexor. The internal 64 kbit/s interface is defined by the functional interface circuits as given in Table 3 The electrical characteristics of the i

10、nterface could be defined by the logic circuits used and are left for further study. The functional interchange circuits may or may not be accessable as a physical interface. (T/CD 02-02). 3.2.2. Intemal 64 Icbitls hiterface (T/CD 02-02). Interchange circuit designation G MT MR MST1 MST2 MSR MLC MLI

11、 MA Interchange circuit name I Signal ground or common return Multiplex channel transmitted data Multiplex channel received data Multiplex channel transmitter signal element timing, mux. source (optional) Multiplex channel transmitter signal element timing, 64 kbit/s bearer source (optional) Multipl

12、ex channel receiver signal element timing Multiplex channel loop No. X control (optional) Multiplex channel loop No. X indicator (optional) Multiplex channel received line signal level detector (optional) I Direction to mux. X X X X from mux. X X X Table 3 (T/CD 02-02). Interchange circuits at the i

13、nternal 64 kbit/s interface. Note: The definitions of the interchange circuits are under study. - Edition of March 15, 1986 CEPT T/CD*02-02*E 2326434 000349b 3 T/CD 02-02 E Page 6 3.3. 4. 4.1. 4.2. 4.2.1 External clock interface (optional) In cases where a clock source external to the multiplexor sy

14、stem is used, the following interchange circuits shall be provided between the multiplexor equipment and the external clock equipment or a clock distribu- tion equipment (see Table 4 / T/CD 02-02). Interchange circuit designation G CE1 CEO Direction Interchange circuit name Signal ground or common r

15、eturn Clock, envelope, incoming Clock, envelope, outgoing) X X Table 4 (T/CD 02-02). Interchange circuits at the external clock interface. Notes: 1) If interchange circuit CE1 is not available, the envelope timing signal has to be detected inside the multiplexor equipment from the incoming 64 kbit/s

16、 multiplexed data stream. In order to provide external tributary transmission equipment with an envelope timing signal, an external clock distribution equipment is inserted between the multiplexor (interchange circuit CEO) and the external tributary trans- mission equipment and provides for the dist

17、ribution of the envelope timing signal. 2) The electrical characteristics at this interface could be in accordance with CCIT Recommendation X.27 (V. 1 i). 3) The multiplexor equipment has an internal clock source which can be synchronized from the 64 kbit/s bearer via interchange circuit MST2. This

18、internal clock source shall guarantee the operation in case of failure of the external clock source, at least to be capable of sending the control informations. 4) The definitions of the interchange circuits are under study. METHOD OF FRAMING Overall structure The residual 4 kbit/s capacity obtained

19、 by carrying the fundamental 60 kbit/s multiplex on the 64 kbit/s bearer shall be distributed so that a padding bit is inserted after each group of 15 bits from the fundamental multiplex (see also Figure 2 (T/CD 02-02). The frame length shall be 2,560 bits in the case of a synchronized bearer, i.e.

20、2,400 bits or 240 envelopes from the fundamental multiplex interleaved with 160 padding bits. When justification is used (for national purposes) in the case of a non-synchronized bearer the last padding bit in the frame can be deleted or an extra padding bit added when needed, resulting in a variabl

21、e frame length of 2,560f 1 bit. (This can allow a maximum speed tolerance of approximately f4 parts in lo4.) The padding bits shall contain the framing pattern, justification service digits and housekeeping signalling (alarms, etc.). Framing Frame alignment patterns The frame alignment method is bas

22、ed on the use of four equidistantly distributed frame alignment patterns written into the padding bits, dividing the frame into four subframes. Each subframe alignment pattern starts with the 14-bit pattern: 11111001101010 followed by a 2-bit subframe identifier unique to the subframe, i.e. : SF1 =

23、00, SF2 = 01, SF3 = 10, SF4 = 11 Edition of March 15, 1986 CEPT T/C.D*02-02*E 79 = 2326414 0003497 5 _ T/CD 02-02 E Page 7 O 640 1280 1920 2560 LO -u LO LIA 40 _IA 40 I I I -y Padding bits in 1 frame (160) X =Justification bit(s) (-, o. o O) Figure 3 (T/CD 02-02). Multiplex frame structure. O, 1, 2

24、bits 4.2.2. Framing strategy 4.2.2. . Loss of frame alignment The criterion for loss of frame alignment shall be three consecutive frame alignment patterns including subframe identiier in error. The frame alignment shall also be considered lost if the rst received frame alignment pattern including s

25、ubframe identifer after reframing is in error. The criterion for reframing shall be the detection of one valid frame alignment pattern. After loss of frame alignment - the outgoing envelopes shall be set to all ONES; - the state shall be signalled to the distant end, and - a parallel hunt for a vali

26、d frame alignment pattern shall be started: After a valid frame alignment pattern is found - the two following padding bits shall be accepted as subframe identifiers and be used to set the frame and subframe counter(s) as applicable; - the blocking of the outgoing data channels shall be removed, and

27、 - the signalling of out of frame alarm to the distant end shall be terminated. 4.2.2.2. Reframing 4.2.2.3. Reframing procedure 5. JUSTIFICATION Justification can be required for national purposes. To achieve this, plus minus justification shall be used in which four repeated justification service s

28、ignals occupy the three bits immediately following each subframe identifier. The last padding bit of the frame is used as a justification digit. The repeated justification service signals are: O10 100 O01 In evaluating the signals in one frame a majority decision of the four received signals is used

29、. In case of no majority, no justifcation shall be assumed. If framing is lost, no justification shall be assumed before reframing has occured. no justification (i.e. one padding bit at end of frame); one justification bit has been added (i.e. two padding bits at end of frame); the justification bit

30、 has been deleted (i.e. no padding bit at end of frame). 6. HOUSEKEEPING SIGNALS AND FUNCTIONS The padding bits not used for framing and justification shall be available for housekeeping information signals, for both international and national use. The definition and allocation of some of the availa

31、ble housekeeping bits is left for further study, The following allocation shall be used. Edition of March 15, 1986 I- _ CEPT T/CD*02-02*E 2326434 0003498 7 TJCD 02-02 E Page 8 6.1. International housekeeping bits Eight bits A, B, C, D, E, F, G, and H are allocated for international housekeeping sign

32、als. The bit A is used to convey to the distant end alarm indications detected at the local end corresponding to : - absence of incoming pulses, - loss of frame alignment; and the bit A shall be assigned such that: - A equals ONE means no alarm, - A equals ZERO means alarm. The other bits B, C, D, E

33、, F, G, and H are reserved to convey further international housekeeping signals. The exact use is under study. Pending the result of the study these bits shall be set to binary ONE. 6.2. Cyclic error-control A cyclic error-control to be used end-to-end on the international 64 kbit/s link is included

34、 as an option. The multiplex frame (2,560 bits) is divided modulo 2 by the polynomial x16 + x12 + x5 + 1 and the resulting reminder (16 bits), the check bits, are sent in the next frame, four bits in each subframe. An error is detected at the receiving end by comparing the check bits generated local

35、ly by dividing the received multiplex frame with the same polynomial, and the check bits received in the following frame. The error detection shall be blocked in the out-of-frame state. 6.3. National housekeeping signals A total of 48 housekeeping bits, 12 in each subframe, remains for national hous

36、ekeeping signals, of which the following are provided: Network status 1- 4 bits Multiplex channel allocation (depending on number of speed classes and coding) 5-10 bits Internal and external alarms 1- 4 bits * These signals could possibly be extended for international use. Housekeeping bits not used

37、 in one network shall be set to binary ONE. For international use multiplexers shall be able to ignore information on national housekeeping bits. The use of national housekeeping bits has to be in accordance with the requirements of the individual Administration. 7. ALLOCATION AND USE OF PADDING BIT

38、S (40 bits) IN ONE SUBFRAME (640 bits) FOR FRAMING, JUSTIFICATION AND HOUSEKEEPING The allocation of padding bits in one subframe numbered P1 to P40 is described below and shown in Figure 3 (T/CD 02-02). P 1 -P4 P5-PX Error check bits 4 bits P9-P20 National housekeeping bits 12 bits P2 1 -P34 Framin

39、g pattern 14 bits P35-P36 Subframe identifier 2 bits For P37-P40 two alternatives exist: International housekeeping bits A, B, C and D Code1 11 11 O0 11 O 1 O 1 O Code 00, 01, 10 or 11 I. Synchronous transmission bearer P37-P40 II. Asynchronous transmission bearer P37-P39 Justification service signa

40、ls P40(P4 1) International housekeeping bits E, F, G, and H Code 001, 010, 100 Justification bit(s) O, 1, 2 bit(s) Code -, O, O0 Only the justification bit(s) in the last subframe (SF4) is used for justification 3 bits Edition of March 15, 1986 CEPT T/CD*02-02*E 79 = 2326414 0003499 9 t:;:;:;:;:;:t

41、1H F SF J X L- b+-b- IH EC NH 4 T/CD 02-02 E Page 9 IH = international housekeeping 4 + 4 bits EC = error-control 4 bits NH = national housekeeping 12 bits F = frame alignment pattern 14 bits SF = subframe identifier 2 bits J = justification service signals 3 bits X = justification bit 1 bit Figure

42、4 (T/CD 02-02). Allocation of padding bits in one subframe (40 bits). 8. TESTING AND MEASURING REQUIREMENTS This item is currently under study (see also Appendices 1 and 2). 9. FAULT CONDITIONS AND CONSEQUENT ACTIONS 9.1. Fault conditions The muldex equipment shall detect the following fault conditi

43、ons : i) Failure of power supply. ii) Failure of timing source. iii) Loss of envelope alignment at a tributary channel interface. iv) Loss of frame alignment at the 64 kbit/s interface. v) An alarm signal, received from the associated muldex equipment at the distant end of a 64 kbit/s link, indicati

44、ng a fault at the associated muldex equipment (see paragraph 9.3. Use of housekeeping bits). vi) Loss of incoming signal at a tributary channel interface. The following conditions, currently under study, may also be recognized as fault conditions and may require subsequent actions : VU) In the event

45、 of a muldex equipment including an error monitor for the examination of the incoming 64 kbit/s composite signals; an alarm could be raised if a certain specific error rate threshold has been exceeded. viii) An alarm may be required to indicate internal buffer overflows. ix) In the event of a muldex

46、 equipment being designed with the capability of checking parity errors, an alarm may be required if such errors are identified. x) Other hardware alarms, e.g. channel card not fully inserted. xi) Loss of incoming signal from line (groupband modem case circuit 109). xii) Detection of AIS at the inte

47、rnal 64 kbit/s interface. 9.2 Consequent actions When a fault condition has been detected, appropriate actions shall be taken as specified in Table 5 (T/CD When the Alarm indication signal (AIS, see Note I) has been detected at the internal 64 kbit/s interface, the local prompt alarm shall optionall

48、y be inhibited. Moreover, AIS or a signal according to X.21/71 shall be sent on all tributary channels. Notes: 1) The Alarm indication signal (AIS) consists of a continuous stream of binary ONES. 2) The alarm is conveyed to the remote end by setting the A bit of each transmitted frame to binary ZERO

49、 condition. 3) When the prompt alarm is not inhibited, the AIS or subsequent loss of frame alignment is regarded as a service alarm, indicating that the data service is interrupted. 4)It is for further study whether the service alarm, detected by means of AIS, should be conveyed in a separate housekeeping bit, e.g. bit B, to the far end. 02-02). Edition of March 15, 1986 r i CEPT T/CD*02-02*E 232b414 0003500 II TICD 02-02 E Page 1 O 1 o. 11. 12. 13. 14. PERFORMANCE The following characteristics should be defined: - error p