BS IEC 61523-4-2015 Design and Verification of Low-Power Integrated Circuits《低功耗集成电路的设计和验证》.pdf

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1、BSI Standards PublicationDesign and Verification of Low-Power Integrated CircuitsBS IEC 61523-4:2015National forewordThis British Standard is the UK implementation of IEC 61523-4:2015.The UK participation in its preparation was entrusted to TechnicalCommittee EPL/501, Electronic Assembly Technology.

2、A list of organizations represented on this committee can be obtained onrequest to its secretary.This publication does not purport to include all the necessary provisions ofa contract. Users are responsible for its correct application. The British Standards Institution 2015.Published by BSI Standard

3、s Limited 2015ISBN 978 0 580 88138 1ICS 25.040; 35.060Compliance with a British Standard cannot confer immunity fromlegal obligations.This British Standard was published under the authority of theStandards Policy and Strategy Committee on 30 April 2015.Amendments/corrigenda issued since publicationD

4、ate Text affectedBRITISH STANDARDBS IEC 61523-4:2015IEC 61523-4 Edition 1.0 2015-03 INTERNATIONAL STANDARD Design and Verification of Low-Power Integrated Circuits INTERNATIONAL ELECTROTECHNICAL COMMISSION ICS 25.040; 35.060 ISBN 978-2-8322-2266-9 Warning! Make sure that you obtained this publicatio

5、n from an authorized distributor. IEEE Std 1801-2013 Registered trademark of the International Electrotechnical Commission xiCopyright 2013 IEEE. All rights reserved.Contents1. Overview 11.1 Scope 11.2 Purpose. 11.3 Key characteristics of the Unified Power Format 11.4 Use of color in this standard 3

6、1.5 Contents of this standard 32. Normative references. 43. Definitions, acronyms, and abbreviations 43.1 Definitions . 43.2 Acronyms and abbreviations . 94. UPF concepts . 114.1 Design structure . 114.2 Design representation 114.3 Power architecture . 144.4 Power distribution 174.5 Power management

7、 234.6 Power states . 264.7 Simstates 294.8 Successive refinement 304.9 Tool flow 314.10 File structure 325. Language basics. 335.1 UPF is Tcl 335.2 Conventions used. 335.3 Lexical elements 345.4 Boolean expressions 375.5 Object declaration 395.6 Attributes of objects. 405.7 Power state name spaces

8、435.8 Precedence . 445.9 Generic UPF command semantics. 455.10 effective_element_list semantics . 455.11 Command refinement 485.12 Error handling 495.13 Units. 506. Power intent commands. 516.1 Categories 516.2 add_domain_elements deprecated 516.3 add_port_state legacy . 526.4 add_power_state . 526.

9、5 add_pst_state legacy . 576.6 apply_power_model. 586.7 associate_supply_set . 59Published by IEC under license from IEEE. 2013 IEEE. All rights reserved. IEC 61523-4 IEEE Std 1801-2013iBS IEC 61523-4:2015xiiCopyright 2013 IEEE. All rights reserved.6.8 begin_power_model 606.9 bind_checker . 616.10 c

10、onnect_logic_net . 636.11 connect_supply_net 646.12 connect_supply_set . 656.13 create_composite_domain 676.14 create_hdl2upf_vct 686.15 create_logic_net 696.16 create_logic_port 706.17 create_power_domain . 716.18 create_power_switch 746.19 create_pst legacy 806.20 create_supply_net . 806.21 create

11、_supply_port 836.22 create_supply_set 846.23 create_upf2hdl_vct 856.24 describe_state_transition . 866.25 end_power_model 876.26 find_objects . 886.27 load_simstate_behavior 906.28 load_upf 916.29 load_upf_protected . 926.30 map_isolation_cell deprecated 936.31 map_level_shifter_cell deprecated 936.

12、32 map_power_switch . 936.33 map_retention_cell 946.34 merge_power_domains deprecated. 976.35 name_format . 986.36 save_upf 996.37 set_design_attributes . 1006.38 set_design_top 1016.39 set_domain_supply_net legacy 1016.40 set_equivalent . 1026.41 set_isolation 1046.42 set_isolation_control deprecat

13、ed. 1106.43 set_level_shifter 1116.44 set_partial_on_translation . 1166.45 set_pin_related_supply deprecated . 1166.46 set_port_attributes . 1176.47 set_power_switch deprecated 1216.48 set_repeater . 1216.49 set_retention 1246.50 set_retention_control deprecated 1286.51 set_retention_elements 1286.5

14、2 set_scope . 1296.53 set_simstate_behavior . 1306.54 upf_version . 1316.55 use_interface_cell . 1327. Power management cell commands. 1357.1 Introduction 1357.2 define_always_on_cell. 1367.3 define_diode_clamp. 137Published by IEC under license from IEEE. 2013 IEEE. All rights reserved. IEC 61523-4

15、 IEEE Std 1801-2013 iiBS IEC 61523-4:2015xiiiCopyright 2013 IEEE. All rights reserved.7.4 define_isolation_cell 1387.5 define_level_shifter_cell 1417.6 define_power_switch_cell .1457.7 define_retention_cell . 1478. UPF processing 1508.1 Overview 1508.2 Data requirements 1508.3 Processing phases 1508

16、.4 Error checking 1539. Simulation semantics . 1549.1 Supply network creation 1549.2 Supply network simulation 1559.3 Power state simulation . 1579.4 Simstate simulation 1599.5 Transitioning from one simstate state to another. 1619.6 Simulation of retention 1629.7 Simulation of isolation. 1689.8 Sim

17、ulation of level-shifting . 1689.9 Simulation of repeater 168Annex A (informative) Bibliography 169Annex B (normative) HDL package UPF 170Annex C (normative) Queries 182Annex D (informative) Replacing deprecated and legacy commands and options. 219Annex E (informative) Low-power design methodology 2

18、27Annex F (normative) Value conversion tables 252Annex G (normative) Supporting hard IP 255Annex H (normative) UPF power-management commands semantics and Liberty mappings. 258Annex I (informative) Power-management cell modeling examples 273Annex J (informative) Switching Activity Interchange Format

19、 303Annex K(informative) IEEE List of Participants333 Published by IEC under license from IEEE. 2013 IEEE. All rights reserved. IEC 61523-4 IEEE Std 1801-2013iiiBS IEC 61523-4:2015xivCopyright 2013 IEEE. All rights reserved.Published by IEC under license from IEEE. 2013 IEEE. All rights reserved. IE

20、C 61523-4 IEEE Std 1801-2013 ivBS IEC 61523-4:2015Published by IEC under license from IEEE. 2013 IEEE. All rights reserved. DESIGN AND VERIFICATION OF LOW-POWER INTEGRATED CIRCUITS FOREWORD 1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization compris

21、ing all national electrotechnical committees (IEC National Committees). The object of IEC is to promote international co-operation on all questions concerning standardization in the electrical and electronic fields. To this end and in addition to other activities, IEC publishes International Standar

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35、ations is indispensable for the correct application of this publication. 9) Attention is drawn to the possibility that implementation of this IEC/IEEE Publication may require use of material covered by patent rights. By publication of this standard, no position is taken with respect to the existence

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38、s entirely their own responsibility. IEC 61523-4 IEEE Std 1801-2013vBS IEC 61523-4:2015Published by IEC under license from IEEE. 2013 IEEE. All rights reserved. International Standard IEC 61523-4/IEEE Std 1801-2013 has been processed through IEC technical committee 91: Electronics assembly technolog

39、y, under the IEC/IEEE Dual Logo Agreement. The text of this standard is based on the following documents: IEEE Std FDIS Report on voting 1801 (2013) 91/1209/FDIS 91/1228/RVD Full information on the voting for the approval of this standard can be found in the report on voting indicated in the above t

40、able. The IEC Technical Committee and IEEE Technical Committee have decided that the contents of this publication will remain unchanged until the stability date indicated on the IEC web site under “http:/webstore.iec.ch“ in the data related to the specific publication. At this date, the publication

41、will be reconfirmed, withdrawn, replaced by a revised edition, or amended. IEC 61523-4 IEEE Std 1801-2013 viBS IEC 61523-4:2015IEEE Std 1801-2013(Revision ofIEEE Std 1801-2009)IEEE Standard for Design and Verification of Low-Power Integrated CircuitsSponsorDesign Automation Committeeof theIEEE Compu

42、ter Societyand theIEEE Standards Association Corporate Advisory GroupApproved 6 March 2013IEEE-SA Standards BoardPublished by IEC under license from IEEE. 2013 IEEE. All rights reserved. IEC 61523-4 IEEE Std 1801-2013viiBS IEC 61523-4:2015Verilog is a registered trademark of Cadence Design Systems,

43、Inc.Grateful acknowledgment is made to the following for permission to use source material:Accellera Systems Initiative Unified Power Format (UPF) Standard, Version 1.0Cadence Design Systems, Inc.Library Cell Modeling Guide Using CPFHierarchical Power Intent Modeling Guide Using CPFSilicon Integrati

44、on Initiative, Inc.Si2 Common Power Format Specification, Version 2.0Abstract: A method is provided for specifying power intent for an electronic design, for use inverification of the structure and behavior of the design in the context of a given power managementarchitecture, and for driving impleme

45、ntation of that power management architecture. The methodsupports incremental refinement of power intent specifications required for IP-based design flows.Keywords: corruption semantics, IEEE 1801, interface specification, IP reuse, isolation, level-shifting, power-aware design, power domains, power

46、 intent, power modes, power states,progressive design refinement, retention, retention strategiesPublished by IEC under license from IEEE. 2013 IEEE. All rights reserved. IEC 61523-4 IEEE Std 1801-2013 viiiBS IEC 61523-4:2015viiiCopyright 2013 IEEE. All rights reserved.IEEE IntroductionThe purpose o

47、f this standard is to provide portable low-power design specifications that can be used with avariety of commercial products throughout an electronic system design, analysis, verification, andimplementation flow.When the electronic design automation (EDA) industry began creating standards for use in

48、 specifying,simulating, and implementing functional specifications of digital electronic circuits in the 1980s, theprimary design constraint was the transistor area necessary to implement the required functionality in theprevailing process technology at that time. Power considerations were simple an

49、d easily assumed for thedesign as power consumption was not a major consideration and most chips operated on a single voltage forall functionality. Therefore, hardware description languages (HDLs) such as VHDL (IEC 61691-1-1/IEEE Std 1076)aand SystemVerilog (IEEE Std 1800) provided a rich set of capabilities necessary forcapturing the functional specification of electronic systems, but no capabilities for capturing the powerarchitecture (how each element of the system is to be powered).As the process technology for