AIR FORCE MIL-HDBK-339-1984 CUSTOM LARGE SCALE INTEGRATED CIRCUIT DEVELOPMENT AND ACQUISITION FOR SPACE VEHICLES《用于航天器的定制大规模集成电路的发展和收购》.pdf

《AIR FORCE MIL-HDBK-339-1984 CUSTOM LARGE SCALE INTEGRATED CIRCUIT DEVELOPMENT AND ACQUISITION FOR SPACE VEHICLES《用于航天器的定制大规模集成电路的发展和收购》.pdf》由会员分享，可在线阅读，更多相关《AIR FORCE MIL-HDBK-339-1984 CUSTOM LARGE SCALE INTEGRATED CIRCUIT DEVELOPMENT AND ACQUISITION FOR SPACE VEHICLES《用于航天器的定制大规模集成电路的发展和收购》.pdf（220页珍藏版）》请在麦多课文档分享上搜索。

1、- YI MIL-HDBK-337 18 m 7777970 0017113 2 T-43 -aq MIL-HDBK-339 (USAF) 31 JULY 1984 MILITARY HANDBOOK CUSTOM LARGE SCALE INTEGRATED CIRCUIT DEVELOPMENT AND ACQUISITION FOR SPACE VEHICLES FSC 1820 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-MIL-HDB

2、K-339 LB 9779770 00171L4 4 i by using the self-addressed Standardization Document Improvement Proposal (DD Form 1426) appearing at the end of this document or by letter. 1 MIL-HDBK-339 (USAF) 31 JULY 1984 DEPARTMENT OF DEFENSE Washington, D. C. 20301 - MIL-HDBK-339 (USAF) 1. This military handbook i

3、s approved for use by all Departments and Agencies of the Department of Defense. 2. Beneficial comments (recommendations, additions, deletions) and any pertinent data which may be of use in improving this document should be addressed to: Space Division SD/ALM Air Force Systems Command P.O. Box 92960

4、 Worldway Postal Center LOS Angeles, CA 90009 5 t 3 c ii Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-a P , i I R I MIL-HDBK-337 3 7977770 0037335 b MIL-HDBK-339 (USAF) 31 JULY 1984 FOREWORD The acquisition of custom large scale integrated circuit

5、s (CLSICs) presents many new and complex technical and management challenges. This handbook is primarily intended to document the design standards and management practices that should be implemented during the acquisition of a high reliability CLSIC for a space system. The requirements are intended

6、to achieve an optimum balance among performance, reliability, and system life cycle cost. The focus is on requirements to assure that the design and manufacturing processes will result in a CLSIC with the desired performance and reliability as contrasted to other possible goals, such as minimizing c

7、hip size or chip cost. The requirements are arranged in sections that correspond to the typical sequence in the acquisition process. By the use of tlshouldll instead of Itshall, II the requirements are intended as guidance rather than contractual compliance. However, adherence to, or deviations from

8、 the tlshouldii requirements could be agenda items at appropriate program reviews. The information inthis handbook is therefore intended to supplement other contractual requirements for reviews, audits, and for part and material controls. To accommodate direct referencing in contractor detailed spec

9、ifications for CLSICs, and to assure appropriate compliance, the requirements in the general specification (Appendix C of this handbook) are stated using llshall.li The selection of a CLSIC implementation instead of an implementation using other devices should be based upon a comparison among the al

10、ternatives of performance, schedule, system life cycle cost, and risk. This comparison should recognize that with another implementation using mature devices, the reliability and performance margins might be better known due to the maturity of the devices used. Also, an implementation using mature d

11、evices might offer other advantages, such as possible alternate suppliers. On the other hand, a CLSIC implementation may offer the possibility for improved performance, much lower power, much less weight, fewer off-chip connections, and lower cost, as compared to other implementations. A CLSIC imple

12、mentation may also offer the possibility.for very high reliability, if it is based on mature design and mature manufacturing concepts. However, the tlcustomtl in CLSIC means that at least some features of a CLSIC may be unique and lack successful usage experience. This lack of maturity is the major

13、problem that may make it difficult, if not impossible. to accuriately predict schedules, performance, (Continued) iii i. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-_ -_ .-_ - MIL-HDBK-337 L M 7979770 00L7Llb MIL-HDBK-339 (USAF) 31 JULY 1984 FORE

14、WORD (Continued) performance margins, and reliability for a CLSIC. In addition, the inherent complexity of a CLSIC makes it difficult to measure all critical performance parameters, or to estimate performance margins, even by testing completed devlces. Meeting the high reliability, performance, and

15、radiation hardness requirements for CLSICs used in space systems is dependent both on the maturity of the major design features and the maturity of the manufacturing processes used. In addition, the quality and reliability margins must be assured at every step during design, simulation, fabrication,

16、 and assembly by the design analysis, processes, and controls used. Therefore, successful acquisitions of high reliability CLSICs may require different and more stringent actions by all participants at every step in the design and manufacturing processes as compared to the acquisition of other devic

17、es. When one performs extensive “front endti audits, design analysis, simulations, documentation, and design reviews, the risks in using CLSICs are expected to be reduced. This handbook is an attempt to document the actions required. Note that although the emphasis in the handbook is on digital devi

18、ces, the handbook is intended to apply to both digital and linear circuitry of CLSICS. Y iv Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,- MIL-HDBK-339 L 9999970 0019117 T m a MIL-HDBK-339 (USAF) 31 JULY 1984 CONTENTS Page 1 . SCOPE 1 1.1 Purpose 1

19、 1.2 Application 1 2 . REFERENCED DOCUMENTS . 3 2.1 Government Documents . 3 3 . DEFINITIONS AND ACRONYMS . 5 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 3.20 3.21 3.22 3.23 3.24 3.25 3.26 3.27 3.28 3.29 3.30 3.31 3.32 3.33 3.34 Absorbed Dose. Total . Accept

20、ance Test Aging Sensitivity ATE Automatic Test Equipment . Basic Circuit Structures . BILBO Built-In Test Built-In Test Features . Built-In Test Structures . Capability Audit . Cell Chip Architecture Chip Behavior Chip Floor Plan Circuit CLSIC . Component Conceptual Design Contracting Officer . i Co

21、ntractor . Control Flow . Controllability Custom Large Scale Integrated Circuit (CLSIC) Data Flow Data Flow Graph Data Flow Language . Design Baseline Design Style . Design Validation Design Verification Designer . Capability Audit Team Design for Testability . V 5 5 5 5 5 5 6 6 6 6 6 6 7 7 7 7 7 7

22、7 8 8 8 9 9 9 9 9 9 10 10 10 10 10 10 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-MIL-HDBK-339 LB 9999970 OOL9LLB L MIL-HDBK-339 (USAF) 31 JULY 1984 CONTENTS (Continued) Page 3.35 3.36 3.37 3.38 3.39 3.40 3.41 3.42 3.43 3.44 3.45 3.46 3.47 3.48 3

23、.49 3.50 3.51 3.52 3.53 3.54 3.55 3.56 3.57 3.58 3.59 3.60 3.61 3.62 3.63 3.64 3.65 3.66 3.67 3.68 3.69 3.70 3.71 3.72 3.73 3.74 3.75 3.76 3.77 3.78 Dynamic Memory . 10 Electron Exposure 11 EMP Induced Pin Transients . 11 End-of-Life Design Limit . 11 Error 11 Error-Detecting/Error-Correcting Code 1

24、1 Failure Mode . 11 Fault 12 Fault Coverage . 12 Fault Detection Test . 12 Fault Location Test 12 Fault Dictionary . 12 Fault Model 12 Fault Population . 12 Fault Resolution . 13 Fault Signature 13 Fault Simulation . 13 Fault Tolerance 13 Firmware . 13 Formal Description . 13 Formal Graphical Descri

25、ption . 14 Free Field Radiation Environment . 14 Functional Test 14 Gray (GY) 14 Hardness Assurance . 14 Hardness Assurance Design Documentation 14 Hardness Noncritical Parts . 14 Hardware Descriptive Language (HDL) 15 Hazard . 15 Initialization . 15 Integrated Circuit . 15 Interface Behavior . 15 K

26、ernel . 15 Large Scale Integrated Circuit (LSIC) 16 Logic Design . 16 Lot (Production Lot. Assembly Lot. and Inspection Lot) . 16 LSIC . 16 LSSD 16 Manufacturer . 16 Manufacturer Surveillance 16 Manufacturing Baseline . 17 Microcode or Microinstruction 17 Microprogram . 17 Mission-Critical Failure .

27、 17 vi Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-I* I MIL-HDBK-339 (USAF) 31 JULY 1984 CONTENTS (Continued) Page 17 3.81 Observability 18 3.83 Parameter Failure Value 18 3.84 Partition 18 3.85 Parts. Materials. and Processes Control Board (PMPC

28、B) . 18 3.86 Parts. Materials. and Processes Selection List . 18 3.87 Petri Net 19 3.88 Pr.A 19 3.89 PMPCB 19 3.90 Process Validation Wafer . 19 3.91 Race Condition 19 3.92 Radiation Characterization . 19 3.93 Radiation Design Margin 19 3.94 Radiation to Failure Method 20 3.95 Radiation Failure Valu

29、e 20 3.96 Radiation Test Facility 20 3.97 RAM 20 3.98 Redundant Subcircuit . 20 3.99 Reqister-Transfer Design . 20 3.100 Reliability . 20 3.102 Scan-In/Scan-Out Design . 21 3.103 Self-checking Circuit . 21 3.105 Single Particle Exposure 21 3.106 Source Control Drawing 21 3.107 Specification Control

30、Drawing 22 3.108 Specified Radiation Environments 22 3.109 State . 22 3.110 Static (Memory) . 22 3.111 Structure . 22 3.112 Stuck-At Fault 22 3.113 Symbolic Simulation . 23 3.116 Test Generation . 23 3.117 Test Pattern 23 3.118 Test Point 23 3.119 Test ProceduLe 24 3.120 Test Requirement Analysis .

31、24 3.121 Test Requirement Document . 24 3.122 Test Response . 24 3.79 MUX (DEMUX) 3.80 Neutron Exposure . 18 3.82 Parameter Design Margin 18 . 3.101 ROM . 20 3.104 Self Test . 21 3.114 Test Analysis 23 . 3.115 Test Chip . 23 vii . Provided by IHSNot for ResaleNo reproduction or networking permitted

32、without license from IHS-,-,-_ . MIL-HDBK-339 L 9797770 OOL9L20 T MIL-HDBK-339 (USAF) 31 JULY 1984 CONTENTS (Continued) Page 3.123 3.124 3.125 3.126 3.127 3.128 3.129 3.130 3.131 3.132 3.133 3.134 3.135 3.136 3.137 3.138 Test Sequence . 24 Test Strategy . 24 Test Structure 24 Test Validation . 24 Te

33、st Vector . 25 Test Verification 25 Testability . 25 Testable Design Methodology . 25 Testable Structural Style . 25 Testing Confidence Level (TCL) . 26 Testing Software 26 Total Dose 26 Variable Sampling Test Method . 26 Very Large Scale Integrated Circuit(s) 26 Wafer Lot . 26 X-Ray. Gamma Ray Expo

34、sures 26 4 . GENERAL REQUIREMENTS . 27 4.1 Justification for Use of CLSICs . 27 4.2 Application . 27 4.2.1 Compliance with System Requirements . 28 4.2.2 CLSIC Selection . 28 4.3 CLSIC Program Plan 28 4.3.1 Testability Assurance Program . 29 4.3.1.1.1 Fault Types . 29 4.3.1.1.2 Testability Measures

35、29 4.3.1.2 Testability Synthesis . 30 4.3.1.2.1 Fault Characterization 30 4.3.1.2.2 Testing Techniques and Strategy . 30 4.3.1.2.3 Intermittent Failure Detection 31 4.3.1.3 Testability Evaluation 31 4.3.2 Product Assurance Program . 31 4.3.2.1 Contractor Product Assurance Program 31 4.3.2.1.1 Manufa

36、cturer Product Assurance Program 31 4.3.2.1.2 Destructive Physical Analysis . 31 4.3.2.1.2.1 Destructive Physical Analysis Management 32 4.3.2.1.2.2 Destructive Physical Analysis Policy. Procedures. and Reports . 32 4.3.2.1.3 Configuration Control . 32 4.3.2.1.4 Source Surveillance . 33 4.3.1.1 Test

37、ability Requirements 29 viii Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-L MIL-HDBK-337 II8 7797770 OOIIYIIZL II 1 MIL-HDBK-339 (USAF) 31 JULY 1984 CONTENTS (Continued) Page 4.4 Role of Parts, Materials, and Processes Control Board. 33 4.5 Progra

38、m and Design Reviews 33 * 4.6 ,atailed Specification 33 4.) Capability Audit 34 4.7.1 Designer Capability Audit - 34 4.7.2 Design Baseline. 34 4.7.3 Manufacturer Capability Audit . 34 4.7.4 Manufacturing Baseline 35 4.8 Hardening and Hardness Assurance Program 35 4.8.1 Hardness Assurance Organizatio

39、n . 35 4.8.2 Hardness Assurance Program Plan . 35 4.8.3 Hardness Assurance Design Documentation . 36 4.8.4 Preliminary and Critical Design Reviews (PDR however, either or both may be entirely separate companies. The separate terms are used in this handbook to distinguish or divide the various respon

40、sibilities specified among ehe user, designer, and manufacturer of CLSICs In this way, the document may be easily tailored for use by either the designer organization or the manufacturer organization. However, this division should not be interpreted as reducing Provided by IHSNot for ResaleNo reprod

41、uction or networking permitted without license from IHS-,-,- MIL-HDBK-337 L 7779770 OOL7L37 5 MIL-HDBK-339 (USAF) 31 JULY 1984 the obligation of the space vehicle contractor to meet all contractual requirements. Nor should the division be interpreted as encouraging or discouraging the same cornpan-,

42、 or different companies, to be the designer, manufacturer, or user. 3.23 CONTROL FLOW Control flow is the specification of when and under what circumstances each function specified in the data flow is performed and, hence, the parallelism to be implemented in the design. Included in the control flow

43、 are precise timing, conditional execution, concurrent operation, state sequencing, and response to error conditions. 3 2 4 CONTROLLAB I LI TY Controllability is a measure of the extent to which signals at any node in a circuit may be controlled using externally applied test signals. 3.25 CUSTOM LAR

44、GE SCALE INTEGRATED CIRCUIT (CLSIC) A custom large scale integrated circuit is a nonstandard monolithic large scale integrated circuit (LSIC) which is designed and fabsicated for a specific system application. 3.26 DATA FLOW Data flow is made up of the set of functions to be performed on data, along

45、 with a specification of input and output variables. Data flow describes variable interactions and potential parallelisms in the behavioral design. The ordering of operations or functions is done on the basis of data precedence. 3.27 DATA FLOW GRAPH A data flow graph consists of a set of nodes inter

46、connected with arcs, where each node represents an operation and the arcs represent flow of data between the operation nodes. 3.28 DATA FLOW LANGUAGE A data flow language expresses data flow in language form and is capable of expressing potential parallelism. 9 Provided by IHSNot for ResaleNo reprod

47、uction or networking permitted without license from IHS-,-,- MIL-HDBK-337 L W 7777770 OOIXl3 7 MIL-HDBK-339 (USAF) 31 JULY 1984 3 29 DESIGN BASELINE The design baseline for CLSICs is a compilation of design tools and design documentation including design guidelines and design rules. 3.30 DESIGN FOR

48、TESTABILITY Design for testability is a process, forming an integral part of a design program, which requires a deliberate effort to ensure that the CLSIC being designed is capable of being tested thoroughly. This should be accomplished with minimum effort and cost, and with minimal impact on reliab

49、ility, resulting in a high testing confidence level. 3.31 DESIGN STYLE Design style refers to a specific organization or architecture in which a basic CLSIC circuit or structure can be implemented. It is usually a function of technology and circuit layout. Examples of design styles for combinational logic are programmable logic arrays (PLAs), read only memor