ISO IEC 24739-2-2009 Information technology - AT Attachment with Packet Interface-7 - Part 2 Parallel transport protocols and physical interconnect (ATA ATAPI-7.pdf

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1、 ISO/IEC 24739-2 Edition 1.0 2009-11 INTERNATIONAL STANDARD Information technology AT attachment with packet interface-7 Part 2: Parallel transport protocols and physical interconnect (ATA/ATAPI-7) ISO/IEC 24739-2:2009(E) THIS PUBLICATION IS COPYRIGHT PROTECTED Copyright 2009 ISO/IEC, Geneva, Switze

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8、abulary online. Customer Service Centre: www.iec.ch/webstore/custserv If you wish to give us your feedback on this publication or need further assistance, please visit the Customer Service Centre FAQ or contact us: Email: csciec.ch Tel.: +41 22 919 02 11 Fax: +41 22 919 03 00 ISO/IEC 24739-2 Edition

9、 1.0 2009-11 INTERNATIONAL STANDARD Information technology AT attachment with packet interface-7 Part 2: Parallel transport protocols and physical interconnect (ATA/ATAPI-7) INTERNATIONAL ELECTROTECHNICAL COMMISSION XE ICS 35.200 PRICE CODE ISBN 2-8318-1071-0 2 24739-2 ISO/IEC:2009(E) CONTENTS FOREW

10、ORD.10 INTRODUCTION.11 1 Scope.12 2 Normative references12 3 Terms, definitions, abbreviations, conventions and keywords 12 3.1 Terms, definitions and abbreviations12 3.2 Abbreviations.21 3.3 Conventions 22 3.3.1 General .22 3.3.2 Precedence .22 3.3.3 Lists 22 3.3.4 Keywords.22 3.3.5 Numbering.23 3.

11、3.6 Signal conventions.24 3.3.7 Bit conventions 24 3.3.8 State diagram conventions.25 3.3.9 Timing conventions26 3.3.10 Byte ordering for data transfers26 3.3.11 Byte, word and DWORD relationships 28 3.4 Relationship of this part of ISO/IEC 24739 to ISO/IEC 24739-1 and ISO/IEC 24739-3 .28 4 General

12、operational requirements .28 5 I/O register descriptions28 6 Command descriptions .28 7 Parallel interface physical and electrical requirements.29 7.1 Cable configuration29 7.2 Electrical characteristics 29 7.2.1 General .29 7.2.2 AC characteristics measurement techniques 31 7.2.3 Driver types and r

13、equired termination.32 7.2.4 Electrical characteristics for Ultra DMA 32 7.3 Connectors and cable asemblies35 7.3.1 General .35 7.3.2 40-pin connector35 7.3.3 4-pin power connector44 7.3.4 Unitized connectors .46 7.3.5 50-pin 65 mm (2.5 in) form factor style connector.48 7.3.6 68-pin PCMCIA connecto

14、r51 7.3.7 48 mm (1.8 in) 3.3 V parallel connector54 7.4 Physical form factors .57 7.4.1 95 mm (3.5 in) form factor57 7.4.2 65 mm (2.5 in) form factor59 7.4.3 48 mm (1.8 in) PCMCIA form factor .64 7.4.4 48 mm (1.8 in) 5 V parallel form factor .64 7.4.5 48 mm (1.8 in) 3.3 V parallel form factor 68 7.4

15、.6 130 mm (5.25 in) form factor69 24739-2 ISO/IEC:2009(E) 3 8 Parallel interface signal assignments and descriptions 73 8.1 Signal summary.73 8.2 Signal descriptions 74 8.2.1 CS(1:0)- (Chip select) 74 8.2.2 DA(2:0) (Device address).74 8.2.3 DASP- (device active, device 1 present).74 8.2.4 DD(15:0) (

16、Device data) 74 8.2.5 DIOR-:HDMARDY-:HSTROBE (Device I/O read:Ultra DMA ready:Ultra DMA data strobe).74 8.2.6 DIOW-:STOP (Device I/O write:Stop Ultra DMA burst)74 8.2.7 DMACK- (DMA acknowledge).75 8.2.8 DMARQ (DMA request)75 8.2.9 INTRQ (Device interrupt) .75 8.2.10 IORDY:DDMARDY-:DSTROBE (I/O chann

17、el ready:Ultra DMA ready:Ultra DMA data strobe).75 8.2.11 PDIAG-:CBLID- (passed diagnostics: cable assembly type identifier)76 8.2.12 RESET- (Hardware reset) 77 8.2.13 CSEL (cable select) .78 9 Parallel interface general operational requirements of the physical, data link and transport layers.79 9.1

18、 Interrupts.79 9.2 Multiword DMA 80 9.3 Ultra DMA feature set 81 9.3.1 Overview .81 9.3.2 Phases of operation.82 9.4 Host determination of cable type by detecting CBLID- 83 10 Parallel interface register addressing 86 11 Parallel interface transport protocol.93 11.1 General 93 11.2 Power-on and hard

19、ware reset protocol 96 11.3 Software reset protocol .100 11.4 Bus idle protocol .105 11.5 Non-data command protocol .116 11.6 PIO data-in command protocol118 11.7 PIO data-out command protocol122 11.8 DMA command protocol126 11.9 PACKET command protocol129 11.10 READ/WRITE DMA QUEUED command protoco

20、l 141 11.11 EXECUTE DEVICE DIAGNOSTIC command protocol145 11.12 DEVICE RESET command protocol.150 11.13 Ultra DMA data-in commands152 11.13.1 Initiating an Ultra DMA data-in burst 152 11.13.2 The data-in transfer.152 11.13.3 Pausing an Ultra DMA data-in burst.152 11.14 Ultra DMA data-out commands155

21、 11.14.1 Initiating an Ultra DMA data-out burst 155 11.14.2 Data-out transfer .155 11.14.3 Pausing an Ultra DMA data-out burst.155 11.14.4 Terminating an Ultra DMA data-out burst.156 4 24739-2 ISO/IEC:2009(E) 11.15 Ultra DMA CRC rules 157 12 Parallel interface timing 159 12.1 Deskewing.159 12.2 Tran

22、sfer timing 159 12.2.1 General .159 12.2.2 Register transfers 159 12.2.3 PIO data transfers .161 12.2.4 Multiword DMA data transfer 164 12.2.5 Ultra DMA data transfer .168 13 Serial interface overview.182 14 Serial interface physical layer182 15 Serial interface link layer.182 16 Serial interface tr

23、ansport layer 182 17 Serial interface device command layer 182 18 Host command layer .182 19 Serial interface host adapter register interface 182 20 Serial interface error handling .182 Annex A (informative) Command Set summary .183 Annex B (informative) Design and programming considertions for larg

24、e physical sector sizes.184 Annex C (informative) Device determination of cable type.185 C.1 Overview 185 C.2 Sequence for device detection of installed capacitor185 C.3 Using the combination of methods for detecting cable type187 Annex D (informative) Signal integrity and UDMA guide188 D.1 General

25、188 D.2 Issues 188 D.2.1 General .188 D.2.2 Timing.189 D.2.3 Crosstalk.195 D.2.4 Ground/power bounce207 D.2.5 Ringing and data settling time (DST) for the 40-conductor cable assembly .208 D.3 System guidelines for Ultra DMA.214 D.3.1 General .214 D.3.2 System capacitance.214 D.3.3 Pull-up and pull-d

26、own resistors 214 D.3.4 Cables and connectors 214 D.3.5 Host PCB and IC design 215 D.3.6 Sender and recipient component I/Os 215 D.4 Ultra DMA electrical characteristics.216 D.4.1 General .216 D.4.2 DC characteristics .216 D.4.3 AC characteristics .218 D.5 Ultra DMA timing and protocol.218 D.5.1 Ult

27、ra DMA timing assumptions .218 D.5.2 Ultra DMA timing parameters.221 D.5.3 Ultra DMA protocol considerations .233 24739-2 ISO/IEC:2009(E) 5 D.6 Cable detection.238 D.6.1 General .238 D.6.2 80-conductor cable assembly electrical feature 238 D.6.3 Host determination of cable assembly type.238 D.6.4 De

28、vice determination of cable assembly type .239 Annex E (informative) Register selection address summary242 Annex F (informative) Sample Code for CRC and Scrambling.244 Annex G (informative) FIS type field value selection .245 Annex H (informative) Physical Layer Implementation Examples.246 Annex I (

29、informative) Command processing Example .247 Bibliography248 Figure 1 ATA document relationships .11 Figure 2 State diagram convention .25 Figure 3 Byte, word and DWORD relationships.28 Figure 4 Ultra DMA termination with pull-up or pull-down 34 Figure 5 Host or device 40-pin I/O header.36 Figure 6

30、40-pin I/O cable connector37 Figure 7 40-pin I/O header mounting 38 Figure 8 40-conductor cable configuration 39 Figure 9 80-conductor ribbon cable.40 Figure 10 80-conductor cable configuration 41 Figure 11 Connector labeling for even or odd conductor grounding .44 Figure 12 Device 4-pin power heade

31、r .44 Figure 13 4-pin power cable connector .45 Figure 14 Unitized connector47 Figure 15 Unitized connector48 Figure 16 50-pin 65 mm (2.5 in) form factor style connector49 Figure 17 48 mm (1.8 in) 3.3 V parallel connector.54 Figure 18 48 mm (1.8 in) 3.3 V parallel host connector .55 Figure 19 95 mm

32、(3.5 in) form factor 58 Figure 20 65 mm (2.5 in) form factor 60 Figure 21 65 mm (2.5 in) form factor mounting holes 62 Figure 22 65 mm (2.5 in) form factor connector location .63 Figure 23 48 mm (1.8 in) 5 V parallel form factor 65 Figure 24 48 mm (1.8 in) 5 V parallel form factor connector location

33、 .67 Figure 25 48 mm (1.8 in) 3.3 V parallel form factor .68 Figure 26 130 mm (5.25 in) HDD form factor 70 Figure 27 130 mm (5.25 in) CD-ROM form factor71 Figure 28 130 mm (5.25 in) CD-ROM connector location.72 Figure 29 Cable select example78 Figure 30 Alternate cable select example .79 Figure 31 E

34、xample configuration of a system with a 40-conductor cable84 6 24739-2 ISO/IEC:2009(E) Figure 32 Example configuration of a system where the host detects a 40-conductor cable.84 Figure 33 Example configuration of a system where the host detects an 80-conductor cable.85 Figure 34 Overall host protoco

35、l state sequence 94 Figure 35 Overall device protocol state sequence .95 Figure 36 Host power-on or hardware reset state diagram 96 Figure 37 Device power-on or hardware reset state diagram.97 Figure 38 Host software reset state diagram.101 Figure 39 Device 0 software reset state diagram.102 Figure

36、40 Device 1 software reset state diagram.104 Figure 41 Host bus idle state diagram.106 Figure 42 Additional Host bus idle state diagram with overlap or overlap and queuing 108 Figure 43 Device bus idle state diagram .111 Figure 44 Additional device bus idle state diagram with overlap or overlap and

37、queuing.113 Figure 45 Host non-data state diagram .117 Figure 46 Device non-data state diagram117 Figure 47 Host PIO data-in state diagram .119 Figure 48 Device PIO data-in state diagram121 Figure 49 Host PIO data-out state diagram .123 Figure 50 Device PIO data-out state diagram125 Figure 51 Host D

38、MA state diagram .127 Figure 52 Device DMA state diagram128 Figure 53 Host PACKET non-data and PIO data command state diagram .130 Figure 54 Device PACKET non-data and PIO data command state diagram 133 Figure 55 Host PACKET DMA command state diagram.136 Figure 56 Device PACKET DMA command state dia

39、gram .139 Figure 57 Host DMA QUEUED state diagram142 Figure 58 Device DMA QUEUED command state diagram 144 Figure 59 Host EXECUTE DEVICE DIAGNOSTIC state diagram.146 Figure 60 Device 0 EXECUTE DEVICE DIAGNOSTIC state diagram.147 Figure 61 Device 1 EXECUTE DEVICE DIAGNOSTIC command state diagram.149

40、Figure 62 Host DEVICE RESET command state diagram150 Figure 63 Device DEVICE RESET command state diagram 151 Figure 64 Example parallel CRC generator .158 Figure 65 Register transfer to/from device 160 Figure 66 PIO data transfer to/from device .162 Figure 67 Initiating a multiword DMA data burst 16

41、5 Figure 68 Sustaining a multiword DMA data burst .166 Figure 69 Device terminating a Multiword DMA data burst.167 Figure 70 Host terminating a multiword DMA data burst168 Figure 71 Initiating an Ultra DMA data-in burst172 Figure 72 Sustained Ultra DMA data-in burst 173 24739-2 ISO/IEC:2009(E) 7 Fig

42、ure 73 Host pausing an Ultra DMA data-in burst.174 Figure 74 Device terminating an Ultra DMA data-in burst 175 Figure 75 Host terminating an Ultra DMA data-in burst176 Figure 76 Initiating an Ultra DMA data-out burst177 Figure 77 Sustained Ultra DMA data-out burst 178 Figure 78 Device pausing an Ult

43、ra DMA data-out burst .179 Figure 79 Host terminating an Ultra DMA data-out burst .180 Figure 80 Device terminating an Ultra DMA data-out burst 181 Figure C.1 Example configuration of a system where the device detects a 40- conductor cable.186 Figure D.1 A transmission line with perfect source termi

44、nation190 Figure D.2 Waveforms on a source-terminated bus with rise time less than T prop .190 Figure D.3 Waveforms on a source-terminated bus with rise time greater than T prop 191 Figure D.4 Waveforms on a source-terminated bus with R_source less than cable Z 0 .192 Figure D.5 Waveforms on a sourc

45、e-terminated bus with R_source greater than cable Z 0 192 Figure D.6 Typical step voltage seen in ATA systems using an 80-conductor cable (measured at drive and host connectors during read).193 Figure D.7 Typical step voltage seen in ATA systems using an 80-conductor cable (measured at host and driv

46、e connectors during write) 194 Figure D.8 Positive crosstalk pulse during a falling edge.196 Figure D.9 Reverse crosstalk waveform from reflected edge.196 Figure D.10 Model of capacitive coupling197 Figure D.11 Waveforms resulting from capacitive coupling (at transmitter and receiver of aggressor an

47、d victim lines)198 Figure D.12 Model of inductive coupling .199 Figure D.13 Waveforms resulting from inductive coupling (at transmitter and receiver of aggressor and victim lines)199 Figure D.14 Model of capacitive and inductive coupling.200 Figure D.15 Waveforms resulting from mixed capacitive and

48、inductive coupling (at transmitter and receiver of aggressor and victim lines) 201 Figure D.16 Model of distributed coupling .202 Figure D.17 Waveforms resulting from distributed coupling (at transmitter and receiver of aggressor and victim lines)202 Figure D.18 Model of voltage divider for connecto

49、r crosstalk formed by PCB and cable.204 Figure D.19 Waveforms showing connector crosstalk dividing between PCB and cable .205 Figure D.20 Model of ground bounce in IC package207 Figure D.21 Waveforms resulting from ground bounce (at transmitter and receiver of aggressor and victim lines)208 Figure D.22 Simple RLC model of 40-con