ISO IEC 14576-1999 Information technology - Synchronous split transfer type system bus (Stbus) - Logical layer《信息技术 同步分离传送类型总线(ST总线) 逻辑层》.pdf

《ISO IEC 14576-1999 Information technology - Synchronous split transfer type system bus (Stbus) - Logical layer《信息技术 同步分离传送类型总线(ST总线) 逻辑层》.pdf》由会员分享，可在线阅读，更多相关《ISO IEC 14576-1999 Information technology - Synchronous split transfer type system bus (Stbus) - Logical layer《信息技术 同步分离传送类型总线(ST总线) 逻辑层》.pdf（94页珍藏版）》请在麦多课文档分享上搜索。

1、INTERNATIONAL STANDARD ISO/IEC 14576 First edition 1999-12 Information technology Synchronous split transfer type system bus (STbus) Logical layer Technologies de linformation Bus de systme de transfert de fente synchrone (STbus) Couche logique Reference number ISO/IEC 14576:1999(E)INTERNATIONAL STA

2、NDARD ISO/IEC 14576 First edition 1999-12 Information technology Synchronous split transfer type system bus (STbus) Logical layer Technologies de linformation Bus de systme de transfert de fente synchrone (STbus) Couche logique PRICE CODE ISO/IEC 1999 All rights reserved. Unless otherwise specified,

3、 no part of this publication may be reproduced or utilized in any form or by any means, electronic or mechanical, including photocopying and microfilm, without permission in writing from the publisher. ISO/IEC Copyright Office Case postale 56 CH-1211 Genve 20 Switzerland X For price, see current cat

4、alogueii 14576ISO/IEC:1999(E) Contents 1. Overview1 1.1 Scope. 1 1.2 Applicability1 2. Definitions. .3 2.1 ExplanationofTerms 3 2.2 Notation.5 3. InterfaceSpecifications 6 3.1 InterfaceSignals 6 4. BusOperations .11 4.1 ProtocolforBasicOperations11 4.2 TransferProtocol .16 4.2.1 Busoperationtypes.16

5、 4.2.2 Commandformat 16 4.2.3 Transfersequence .25 4.3 Arbitration.27 4.4 StatusReports27 4.5 DataTransfer .29 4.5.1 Memoryaccess(write)29 4.5.2 Memoryaccess(read) .35 4.5.3 Controlspaceaccess(write) .38 4.5.4 Controlspaceaccess(read).40 4.5.5 Messagetransfer 42 4.5.6 Controlregisteraccess(write) 44

6、 4.5.7 Controlregisteraccess(read)46 4.6 LockOperations 48 4.7 CacherelatedOperations.50 4.7.1 Cacheinvalidation 50 4.7.2 Retryindication.53 4.7.3 Copybackandstealoperationsafterretryindication55 4.7.4 Stealinhibitoperation.57 4.8 ErrorHandling.59 4.8.1 Handlingerrorsnotifiedinanswer .59 4.8.2 Other

7、errordetection .6114576ISO/IEC:1999(E) iii 5. CacheCoherencyControl 62 5.1 CacheControlMethods.62 5.2 CacheBlockAttributes62 5.3 OperationsonSystemBus.63 5.4 RetryIndication .65 5.5 StealOperation 66 5.6 CacheDataManagementandStateTransition67 5.6.1 Writethroughcache67 5.6.2 Copybackcache 70 5.7 Not

8、esonMemoryAccess75 6. FunctionsforEnhancedReliability76 6.1 Redundancy.76 6.2 DetectingFaults.77 6.3 PreventingFaultsfromSpreading .77 6.4 SupportingFaultHandlingandDiagnosis 78 AnnexA(informative) Performance(Estimated) 79 AnnexB(informative) Returnofanswerinalocktransfer .80 AnnexC(informative) Lo

9、cktransferandwritebackofcopybackcache 81iv 14576ISO/IEC:1999(E) Figures Figure1STbusApplications .2 Figure2Connectioninterfacebetweenfunctionunits(basicpattern) 7 Figure3Conceptofbusoperationprotocol(for1cycleor2cycletransfer: 8bytebuswidthspecification,writeoperation) 11 Figure4Conceptofbusoperatio

10、nprotocol(fortransferof3cyclesormore: 8bytebuswidthspecification,readoperation)13 Figure5Conceptofbusoperationprotocol(for1cycleor2cycletransfer: 4bytebuswidthspecification,writeoperation) 15 Figure6Pipelineoperation20 Figure7BCTfield.21 Figure8RAandbytealignment23 Figure9a)Onewordmemorywrite(noansw

11、ertransaction) 31 Figure9b)Onewordmemorywrite(basictransaction).32 Figure9c)nwordmemorywrite(noanswertransaction) .33 Figure9d)nwordmemorywrite(basictransaction) .34 Figure10a)Onewordmemoryread.36 Figure10b)nwordmemoryread.37 Figure11nwordwrite:controlspaceaccess39 Figure12nwordread:controlspaceacce

12、ss .41 Figure13nwordmessagetransfer43 Figure14Onewordwrite:controlregisteraccess 45 Figure15Onewordread:controlregisteraccess .47 Figure16Buslocktransfer49 Figure17Cacheinvalidation.52 Figure18Retryindication .54 Figure19Copybackandstealoperationsafterretryindication 56 Figure20Stealinhibitoperation

13、 .58 Figure21ErrorreportinanswertransactionwhenDUTdetectserror .60 Figure22Whenfunctionunit(0#)detectstimeout61 Figure23RelationbetweenCPUoperationandcommandsonsystembus .64 Figure24STbuswritethroughcachecoherencycontrolprotocol69 Figure25STbuscopybackcachecoherencycontrolprotocol 74 FigureA.1STbusp

14、erformance(in8bytebuswidthand32bitaddressingmode)79 FigureB.1Exampleofdeadlockproblem 80 FigureC.1ExampleoflocktransfertoEMcachedata.8114576ISO/IEC:1999(E) v Tables Table1BasicInterfaceSignals(functionunitinterfacesotherthanbushandler) .6 Table2OptionalInterfaceSignals(functionunitinterfacesothertha

15、nbushandler) .6 Table3CommandFormatforInformationTransferBus17 Table4OPTCodeDefinitions 18 Table5MBitDefinition .19 Table6MessageSequence 22 Table7AnswerCodeDefinition .28 Table8SystemBusCommandTypes.63 Table9SemanticsofDiscrepancybetweenBaseandSpareSignals76vi 14576ISO/IEC:1999(E) INFORMATIONTECHNO

16、LOGY SYNCHRONOUSSPLITTRANSFERTYPE SYSTEMBUS(STbus) LOGICALLAYER FOREWORD ISO(theInternationalOrganizationforStandardization)andIEC(theInternational ElectrotechnicalCommission)formthespecializedsystemforworldwide standardization.NationalbodiesthataremembersofISOorIECparticipateinthe developmentofInte

17、rnationalStandardsthroughtechnicalcommitteesestablishedby therespectiveorganizationtodealwithparticularfieldsoftechnicalactivity.ISOand IECtechnicalcommitteescollaborateinfieldsofmutualinterest.Otherinternational organizations,governmentalandnongovernmental,inliaisonwithISOandIEC,also takepartinthew

18、ork. Inthefieldofinformationtechnology,ISOandIEChaveestablishedajointtechnical committee,ISO/IEC JTC 1.DraftInternationalStandardsadoptedbythejoint technicalcommitteearecirculatedtonationalbodiesforvoting.Publicationasan InternationalStandardrequiresapprovalbyatleast75%ofthenationalbodiescasting avo

19、te. InternationalStandardISO/IEC14576waspreparedbysubcommittee26: Microprocessorsystems,ofISO/IECjointtechnicalcommittee1:Information technology. InternationalStandardsaredraftedinaccordancewiththerulesgivenintheISO/IEC Directives,Part3. AnnexesA,BandCareforinformationonly.14576ISO/IEC:1999(E) 1 INF

20、ORMATIONTECHNOLOGY SYNCHRONOUSSPLITTRANSFERTYPE SYSTEMBUS(STbus) LOGICALLAYER 1. Overview 1.1Scope ThisInternationalStandardspecifiesthelogicalspecificationsofSTbuswhichisahigh performanceandhighlyreliablesystembus.STbusadoptsasynchronoustransfermethodwitha highspeedclockandasplittransfermethodenabl

21、ingtominimizebusholdingtimeduringone busoperationandtouseabusefficiently. Thecontentsgiveninthisspecificationsareasfollows: a)Systembusinterfacesignalprovisions; b)Busoperationsandtransferprotocolforeachbusoperation; c)Copybackcachecoherencycontrolformaintainingconsistencybetweenasharedmemoryand aca

22、chememoryofeachprocessorinamultiprocessorsystem; d)Faultdetectionfunctionusingparitycheckandduplexconfigurationforcontrolsignals. 1.2Applicability ThisInternationalStandardisApplicabletoahighperformancesystembusoranI/Obusina multiprocessorsystem.TypicalSTbusapplicationsareindicatedinFigure1: a)ASyst

23、embusandanI/ObusinaTCMPsystem; b)ASystembusinanLCMPsystem. TCMP:tightlycoupledmultiprocessorsystem (Asystemconsistingoftwoormoreprocessorssharingthesamememory,withthe entiresystemcontrolledbyoneOS.) LCMP:looselycoupledmultiprocessorsystem (Asysteminwhicheachprocessorisconnectedbyasharedmemoryorother

24、medium, witheachprocessoroperatedbyanindividualOS.)2 14576ISO/IEC:1999(E) Figure1STbusApplications CPU CPU Shared memory System bus I/Obus I/O I/O TCMP system Processor Localmemory LCMP system Localmemory CPU CPU LocalI/O LocalI/O Systembus Processor Processor Processor . . .14576ISO/IEC:1999(E) 3 2

25、. Definitions 2.1 ExplanationofTerms ForthepurposesofthisInternationalStandard,thefollowingtermsanddefinitionsapply. 1) Answertransaction Aninformationtransferoperationbywhichafunctionunitreceivingacommandreturns answerinformation,tonotifytheunitissuingthecommandthatthecommandhasbeen completed(insom

26、ecasestherequesteddataisappended)andtoindicatestatusinformation. 2) Basicsignal ThosebusinterfacesignalsthatmustbeimplementedineverySTbussystem,andthusfor whichcompatibilityisassuredamongdifferentsystems. 3) Block Theminimumunitregisteredincachememory.InSTbusthisislimitedto32bytes. 4) Bushandler(BH)

27、 Aconcentratedbuscontrolmechanismforsortingoutcompetingbusrequestsfromdifferent functionunits,selectingoneoftherequests,andgrantingthebusrighttothatfunctionunit. 5) Busmaster Afunctionunitthathasthebusright(agrantsignalhasbeenasserted)andistransferring informationonthebus. 6) Busslave Afunctionunitt

28、owhichinformationisbeingtransferredbythebusmaster. 7) Bussnoop Monitoringofthebusforreadoperationsfromexternalmemoryandwriteoperationsto externalmemory. 8) Cacheinvalidation Arequesttoinvalidateablockincachememory.Forexample,whenawriteaccessismade toaShared&Unmodified(SU)area,thisisusedtoinvalidatet

29、hesameareainanother cache. 9) CPU Acentralprocessingelementwithfunctionsforinterpretingandexecutinginstructions.In thesespecifications,cachememoryisincludedwiththeCPU. 10)Copybackscheme Acacheupdatingmethodinwhichdatawrittenbytheprocessororinstructionexecution partisupdatedonlyinthecache,withoutbein

30、greflecteddirectlyinmemory.Thecopyback4 14576ISO/IEC:1999(E) cachesupportedinSTbushasthefollowingthreeinternalstates:Invalidstate(I),Shared& Unmodifiedstate(SU),Exclusive&Modifiedstate(EM). 11)DUT(DestinationUnit) Afunctionunitperformingananswertransaction. 12)Exclusive&Modifiedstate(EM) Aninternals

31、tateinacopybackcache,wherebytheonlyplaceinthesystemanaccessareais registeredisincachememory,andthecontentsarenotthesameassharedmemory.Inthis state,onlythecachehasbeenupdated. 13)Functionunit Ahardwareunitconnectedtothebusandhavingamechanismforbusinterfacecontrol. Normallyonefunctionunitconsistsofone

32、board. 14)I/Oadapter AfunctionunitthatcontrolsI/Odevicesundercontrolofaprocessor. 15)Invalidstate(I) Astateinwhichanareaaccessedbytheprocessorisnotregisteredincachememory. 16)Modifiedreadcommand Acommandissuedtothesystembusbyacopybackcachememorywhenawriteaccessby theprocessorresultsinawritemiss. 17)

33、Optionalsignal Thosebusinterfacesignalsthatusersarefreetoadoptornotinsystemimplementation. 18)Ordertransaction Aninformationtransferoperationforsendingacommandandrequestingprocessingby anotherfunctionunit. 19)Parity Whennototherwisenotedinthesespecifications,parityisalwaysodd.Hereoddparity meansthat

34、whenagivensignal(e.g.,8bits)isaugmentedbyaparitybit(e.g.,8+1=9 bits),thenifthesumof1bitsintheaugmentedsetisanevennumber(including0)anerror isdetected. 20)Processor AfunctionunitwiththecapabilityofexecutinginstructionsandcontrollingthevariousI/O adapters.ProcessorconsistsofCPUandmemoryingeneral. 21)R

35、eadhit/readmiss Whenaninstructionoroperandtobereadbytheprocessorisregisteredincachememory, thisiscalledareadhit.Ifnot,itisareadmiss.14576ISO/IEC:1999(E) 5 Inthecaseofareadmiss,iftheobjectofthereadiscacheable,oneblockcontainingthe objectisnewlyregisteredinthecache. 22)Retryindication Thetemporarysusp

36、ensionofaccessbyexternaldevicestoacopybackcacheareathathas beenupdatedwithoutthechangehavingbeenreflectedinmainmemory. 23)Shared&Unmodifiedstate(SU) Aninternalstateinawritethroughorcopybackcache,wherebyanaccessareaisregistered inacacheandhasthesamecontentsassharedmemory.Sharingbymorethanonecacheis p

37、ossible. 24)SUT(SourceUnit) Afunctionunitperforminganordertransaction. 25)Writehit/writemiss Ifanareatobewrittenbytheprocessorisregisteredincachememory,thisiscalledawrite hit.Ifnot,itisawritemiss. Inthecaseofawritethroughcache,thewritedataisimmediatelyreflectedinshared memory. Ifacopybackcachescheme

38、isused,inthecaseofawritehitthewritedataisreflectedinthe cacheonly.Ifawritemissoccurs,oneblockofthewriteareaisreadfromsharedmemory andnewlyregistered,thenthewritedataiswrittenoverthatareainthecacheonly. 26)Writethroughscheme Acacheupdatingmethodinwhichdatawrittenbytheprocessororinstructionexecution p

39、artisreflecteddirectlyinmemory.Theinternalstatesare:Invalidstate(I),Shared& Unmodifiedstate(SU). 2.2 Notation Thefollowingsymbolsandothernotationareusedinthesespecifications. Functionunitnumbersareindicatedby(#n),andcontrolsignalstoeachunitarewrittenas signallinename+(functionunitnumber),e.g.,RQL*(#

40、n),GR*(#n). Whenthevaluesofcontrolsignalsareindicated,thefollowingnotationisused. Whenindicatingthelogicalvalueofasignalline:1and0areused,with1meaningassert and0meaningnegate. Whenindicatingtheactualvalueonasignalline:“H“and“L“areused,with“H“ meaninghighand“L“meaninglowsignalpotential. Hexadecimalno

41、tationinthesespecificationsisindicatedbyH#(e.g.,HFF,H00).6 14576ISO/IEC:1999(E) 3. InterfaceSpecifications 3.1 InterfaceSignals TheSTbusbasicinterfacesignalsarelistedinTable1,asseenfromonefunctionunit. Inthistable,RQL*,RQH*,GR*,andET*aresignalsconnectedindividuallytoeachfunction unit. Table1BasicInt

42、erfaceSignals(functionunitinterfacesotherthanbushandler) No. Signalname Count Functionalcategory Connectiontype 1R Q L * (Request low) 1 2R Q H * (Requesthigh) 1 Arbitrationcontrol Individually 3G R * (Grant) 1 connected 4ET * (Endofbustransaction) 1 5B S * (Bustransactionstart) 1 6B U R * (Burst) 1 Transfercontrol 7C S P * (Control signal parity) 1 8L C K * (Lock) 1 Bus connection 9 AD0063 * (Command/address/data) 64 Command/address/data 10 ADP07 * (ADparity) 8 11 RTY * (Retry) 1 Cachecoherencycontrol 12 RST * (Reset) 1 Resetsignal 13 CK (Clock) 1 Clock SeeNote2. Totalnumberofsignals 83 Note