TIA-612-1993 Electrical Characteristics for an Interface at Data Signaling Rates up to 52 Mbit s《在数据信令高达52 Mbit s的接口的电气特性》.pdf

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1、 TIA/EIA-612-1993 APPROVED: NOVEMBER 2, 1993 REAFFIRMED: SEPTEMBER 10, 1999 REAFFIRMED: SEPTEMBER 14, 2005 REAFFIRMED: JULY 29, 2014 TIA-612 December 1993Electrical Characteristics for an Interface at Data Signaling Rates up to 52 Mbit/s NOTICE TIA Engineering Standards and Publications are designed

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20、S. EIA TIA-bL2 93 = 3234600 0552390 4b7 ELECTRICAL CHARACTERISTICS FOR AN INTERFACE AT DATA SIGNALING RATES UP TO 52 Mbis (From Standards Proposai Nos . 2795. 2795-1 and 2795.2. formulated under the cognizance of TIA TR30.2 Subcommittee on Data Transmission Interfaces) Contents Page 1 2 3 3.1 3.1.1

21、3.1.2 3.1.3 3.1.4 3.2 3.2.1 O 3.2.2 3.2.3 3.2.4 3.3 4 5 SCOPE 1 APPLICABILITY . 2 ELECTRICAL CHARACTERISTICS . 3 Generator Characteristics 3 Open Circuit Measurement . 4 Output Signal Waveform 6 Test Termination Measurements . 5 Short Circuit Measurement 5 Load Characteristics . 7 Input Current-Volt

22、age Measurements . 7 Input Sensitivity Measurements 7 Failsafe Operation . 9 Cable Termination . 9 Interconnecting Cable Electrical Characteristics . 10 ENVIRONMENTAL CONSTRAINTS . 10 CIRCUIT PROTECTION 11 Annex A (informative) . 12 A . 1 A.l.l Length 12 A.1.2 Cable Physical Characteristics 12 A.1.3

23、 Cable Termination . 12 A.2 A.2.1 A.2.2 Interconnecting Cable 12 ECL Generators and Receivers 13 ECL - Emitter Coupled Logic Technology 13 Failsafe Biasing of Receivers . 13 Annex B (informative) . 14 References 14 a i EIA TIA-612 93 m 3234600 0552191 3T3 m This Page Intentionally Left Blank EIA TIA

24、-h32 93 m 3234h00 0552392 23T = FOREWORD (This foreword is not part of this Standard) This Standard was formulated under the cognizance of TIA Subcommittee TR-30.2 on Data Transmission Interfaces. It is intended to be used with ANSIKIAEIA-613-1993, High Speed Serial Interface for Data Terminal Equip

25、ment and Data Circuit- Terminating Equipment. This Standard specifies generators and receivers capable of operating at data signaling rates up to 52 Mbits. This Standard was developed in response to a demand from the data communications community for a high speed general purpose DTE-DCE interface. A

26、nnex A of this Standard is informative and provides guidelines for application. Annex B of this Standard is also informative and provides references to this Standard. Neither Annex is considered part of this Standard. I iii EIA TIA-bL2 93 323YbOO 0552393 376 This Page Intentionally Left Blank iv EIA

27、 TIA-b32 93 m 3234600 0552394 O02 m ANSI/TIA/EIA-612-1993 1 SCOPE This Standard sDecifies the electrical characteristics of the balanced diaital interface circuit, normally implemented in integrated circuit technology, ?hat may be employed when specified for the interchange of serial binary signals

28、between Data Terminal Equipment (DTE) and Data Circuit-Terminating Equipment (DCE) or in any point-to-point interconnection of serial binary signals between data equipments. The interface circuit includes a generator connected by a balanced interconnecting cable to a load consisting of a receiver an

29、d a termination. The electrical characteristics of the circuit are specified in terms of required voltage, and current values obtained from direct measurements of the generator and receiver components at the interface points. The logic function of the generator and the receiver is not defined by thi

30、s Standard, as it is ap pl cat io n -dependent. Minimum electrical requirements for the interconnecting cable are f u rnis h ed. It is intended that this Standard will be referenced by ANSI/TIA/EIA-613-1993, High Speed Serial Interface for Data Terminal Equipment and Data Circuit- Terminating Equipm

31、ent, that specifies the other necessary components of an interface (e.g., connector, pin assignments, function) for applications where the electrical characteristics of a high speed balanced digital circuit are required. 1 EIA TIA-bL2 93 3239600 0552195 T49 D D T E ANSI/TIA/EIA-612-1993 D C E 2 APPL

32、ICABILITY Id L The provisions of this Standard may be applied to the circuits employed at the interface between equipments where information being conveyed is in the form of binary signals. Typical points of applicability for this Standard are depicted in figure 1. Legend: DTE = Data Terminal Equipm

33、ent DCE = Data Circuit-Terminating Equipmc E = Interface Generator = Interface Receiver = Balanced Interface Circuit - Figure 1 - Applications of balanced digital interface circuit The balanced digital interface circuit will normally be utilized on data and timing, or control circuits where the data

34、 signaling rate is up to a maximum limit of 52 Mbis. In this Standard, the term: data signaling rate, expressed in the units bit/s (bits per second), is the significant parameter. It may be different from the equipments data transfer rate, which employs the same units. Data signaling rate is defined

35、 as 1/T where T is the minimum interval between two significant instants. In a binary system for which this Standard is designed, the data signaling rate in bitk and the modulation rate in bauds are numerically equal when the unit interval used in each determination is the minimum interval. star (*)

36、 represents the opposite input condition for a parameter. For example, the symbol Q represents the receiver output state for one input condition, while Q represents the output state for the opposite input state. 2 EIA TIA-bL2 93 3234600 055219b 985 = ANSITTINEI-612-1993 3 ELECTRICAL CHARACTERISTICS

37、The balanced digital interface circuit is shown in figure 2. The circuit consists of three parts: the generator (G), the balanced interconnecting cable, and the load. The load is composed of a receiver (R) and a cable termination/faiIsafe network. The electrical Characteristics of the generator and

38、receiver are specified in terms of direct electrical measurements while the interconnecting cable is described in terms of its electrical characteristics. + GENERATOR )+BALANCED INTERFACL LOAD b Cable CABLE Vee B 755- B 1 Rt = 110 R Rrp = Q 1.5 k(l I I Legend: G = Generator Rgp = Generator Pull Down

39、 Resistor R = Receiver Rt = Termination Resistor Rrp = Receiver Bias Resistor (Optional, Receiver Dependent) Vcpd = Common Potential Difference Vee = Negative Voltage Power Supply NOTE: All resistors f 2% A,B = Generator Interface Points A,B = Receiver Interface Points C = Generator Circuit Common C

40、 = Receiver Circuit Common Figure 2 - Balanced digital interface circuit 3.1 Generator Characteristics The generator electrical characteristics are specified in accordance with the measurements illustrated in figures 3 to 6 and described in 3.1.1 through 3.1.4. The generator circuit meeting these re

41、quirements results in a low impedance 3 EIA TIA-bL2 93 m 3234b00 0552377 BLL ANSITTINEIA-612-1993 balanced source that will produce a differential voltage applied to the interconnecting cable in the range of 590 mV to 1500 mV. The signaling sense of the voltages appearing across the interconnecting

42、cable are defined as follows: a. The A terminal of the generator shall be negative with respect to the B terminal for a binary O (SPACE or OFF) state. b. The A terminal of the generator shall be positive with respect to the B terminal for a binary 1 (MARK or ON) state. NOTE -, The sense of data bina

43、ry O (SPACE) and data binary 1 (MARK) are inverted from that specified in ElMIA-422-A. The logic function of the generator and the receiver is beyond the scope of this Standard, and therefore is not defined. 3.1.1 Open Circuit Measurement (Figure 3) For either binary state, the magnitude of the diff

44、erential voltage (VOC or VOC) measured between the two generator output terminals shall not exceed 1.5 V. Vee T- OPEN CIRCUIT MEASUREMENT I VOC I 51.5 v, I VOC I 5 1.5 V 0 = Measured Parameter I Vee Figure 3 - Open circuit measurement 4 ANSITTINEIA-612-1993 3.1.2 Test Termination Measurements (Figur

45、e 4) With a test load of the resistors shown in figure 4, the magnitude of the differential output voltage (Vt), shall be 590 mV or greater. For the opposite binary state, the polarity of Vt shall be reversed (Vt*). The magnitude of the difference between Vt and Vt shall be less than 100 mV. The mag

46、nitude of the generator offset voltage (Vos), measured between the center point of the test load and the generator circuit common shall be -1.6 V or more positive for either binary state. The magnitude of the difference of Vos for one binary state and Vos for the opposite binary state shall be 1 O0

47、mV or less. Vee TEST TERMINATION MEASUREMENTS I Vt I 2 590 mV, I Vt I 2 590 mV I I Vt I - I Vt I I I 100 mV I Vos - Vos I I 100 mV = Measured Parameter O V 2 VOS 2 -1.6 V, O V 2 VOS 2 -1.6 I Vee Figure 4 - Test termination measurements 3.1.3 Short-Circuit Measurement (Figure 5) With the generator ou

48、tput terminals short-circuited to each other, the magnitude of the current (los) following between each output terminal shall not exceed 50 mA in magnitude, for either binary state. SHORT CIRCUIT MEASUREMENT I los I s 50 mA, I los I I50 mA = Measured Parameter Vee Figure 5 - Short-circuit measuremen

49、t 5 EIA TIA-bL2 73 3234600 0552377 b74 ANSI/TIA/EIA-612-1993 3.1.4 Output Signal Waveform (Figure 6) During transitions of the generator output between alternating binary states (one-zero-one-zero, etc.), the differential voltage measured across the 1 1 O Q test load connected between the generator output terminals shall be such that the voltage monotonically changes between 0.2 and 0.8 of Vss within 0.5 ns to 2.3 ns. Thereafter, the signal voltage shall not vary more than 10% of Vss from the steady state value, until the next binary transition occurs, and at no tim