SMPTE RP 198-1998 Bit-Serial Digital Checkfield for Use in High-Definition Interfaces《高清晰接口中使用的位串行数字检验区》.pdf

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1、STD=SMPTE RP 178-ENGL L77B 8357901 0003OOL LBO SMPTE RECOMMENDED PRACTICE RP 198-1 998 Bit-Serial Digital Checkfield for Use in High-Definition Interfaces 1 Scope This practice specifies digital test signals suitable for evaluating the low-frequency response of equip ment handling high-definition se

2、rial digital video signals as defined in ANSVSMPTE 292M. Although a range of signals will produce the desired low- frequency effects, two specific signals are defined to test cable equalization and phase locked loop (PLL) lock-in, respectively. In the past, these two signals have been colloquially c

3、alled “pathological signals.“ 2 General considerations Stressing of the automatic equalizer is accomplished by using a signal with the maximum number of ones or zeros, with infrequent single clock period pulses to the opposite level. Stressing of the phase locked loop is accomplished by using a sign

4、al with a maximum low-frequency content; that is, with a maximum time between level transitions. 2.1 Channel coding of the serial digital signal defined by ANSVSMPTE 292M utilizes scram- bling and encoding into NRZI (nonreturn to zero, inverted) accomplished by a concatenation of the two following f

5、unctions: GI (X)=X9+X4+1 G2(X) = X + 1 As a result of the channel coding, long runs of zeros in the G2 (X) output data can be obtained when the scrambler, GI (X), is in acertain state at the time when the specific words arrive. That certain state will be present on a regular basis; therefore, contin

6、uous application of the specific data words will regularly produce the low-frequency effects (see annex A). 2.2 Although the longest run of parallel data zeros (40 consecutive zeros) will occur during Page 1 of 4 pages the EAV/SAV TRS words, the frequency with which the scrambling of the TRS words c

7、oincide with the required scrambler state to permit either stressing condition is low. In the instances where this coincident occurs, the generation of the stressing condition is so time limited that equalizers and phase locked loops are not maxi- mally stressed. 2.3 In the data portions of digital

8、video signals (excluding TRS words in EAVs or SAVs, and ANC data flag words), the sample values are restricted to exclude data levels O to 3 and 1020 to 1023 (OOOh to 003h and 3Fch to 3FFh in 1 O-bit hexadecimal representation and 00.0 to 0O.C and FF.0 to FF.C, in 8.2 hexadecimal notation). The resu

9、lt of this restriction is that the longest run of zeros, at the scrambler input, is 16 (bits), occurring when a sample value of 200h is followed by a value between 004h and 007h. This situation can produce up to 26 consecutive zeros at the NRZI output, which is (also) not a maxi- mally stressed case

10、. 2.4 Other specific data words in combination with specific scrambler states can produce a repetitive low-frequency serial output signal until the next EAV or SAV affects the scrambler state. It is these combinations of data words that form the basis of the test signals defined by this practice. 2.

11、5 Because of the Y/C interleaved nature of the component digital signal, it is possible to obtain nearly any permutation of word pair data values over the entire active picture area by defining a particular flat color field in a noise-free environ- ment. Certain of these permutations of word pair da

12、ta values will produce the desired low- frequency effects. Copyright O 1998 by the SOCIETY OF MOTION PICTURE AND TELEVISION ENGINEERS 595 W. Hartcdale Ave., White Plains, NY 10607 (914) 761 -1 1 O0 Approved January 1,1998 STD-SMPTE RP 174-ENGL 1998 m l5357q01 0003002 o17 m RP 198-1 998 3 Checkfield

13、data 3.1 Receiver equalizer testing is accomplished by producing a serial digital signal with maxi- mum dc content. Applying the sequence 300h, 198h (CO.0, 66.0) continuously to the C and Y samples (respectively) during the active line will produce a signal of 19 consecutive high (low) states follow

14、ed by one low (high) state in a re- petitive manner, once the scrambler attains the required starting condition. Either polarity of the signal can be realized, indicated by the level of the 19 consecutive states. By producing approximately half of a field of continuous lines containing this sequence

15、, the required scram- bler starting condition will be realized on several lines, and this will result in the generation of the desired equalizer testing condition. 3.2 Receiver phase locked loop testing is accomplished by producing a serial digital signal with maximum low-frequency content and minim

16、um high-frequency content (.e., lowest frequency of level transitions). Applying the sequence 200h, 11 Oh, (80.0, 44.0) continuously to the C and Y samples (respectively) during the active line will produce a signal of 20 consecu- tive high (low) states followed by 20 low (high) states in a repetiti

17、ve manner, once the scrambler attains the required starting condition. By pro- ducing approximately half of a field of continuous lines containing this sequence, the required scrambler starting condition will be realized on several lines, and this will result in the genera- tion of the desired phase

18、 locked loop testing condition. 3.3 Because the equalizer test works by producing a serial digital signal with a dc bias, steps must be taken to ensure that both polarities of dc bias are realized. To change the polarity of the dc bias from one frame to the next, the sum total of all the bits in all

19、 the data words in all the lines in a video field must be odd. To ensure that the polarity of the bias can change often, a single Y sample data word in the signal is changed from 198h to 19Oh (a net change of 1 data bit), once every other frame. This causes the bias polarity to alternate at a frame

20、rate regardless of whether the original frame bit sum is even or odd. The data word in which the value substitution is made is the first Y sample in the first active picture line of every other frame. The specific word and line for each signal format is listed in table 1 as the polarity control word

21、. 3.4 The sequence 300h, 198h (CO.0, 66.0) and 200h, 11 oh (80.0,44.0) applied to C and Y samples results in shades of purple and gray, respec- tively. Reversing the C and Y ordering for each of these two sequences results in lighter and darker shades of green, respectively. Table 1 illustrates one

22、ordering of each of the two se- quences, but either ordering of the data values for each sequence is permitted by this practice. If the ordering described in 3.1 is reversed, then the polarity control word described in 3.3 is changed to 200h (80.0). The polarity control word in either case is locate

23、d at the first Y sample in the first active picture line in the field(s) specified in 3.3. 4 Serial digital interface (SDI) checkfield Distribution of data in the SDI checkfield is shown in figurel for the signal standards referenced in annex A. Specific distributions of sample values are shown in t

24、able 1. In each field, the line where the signal transitions from the equalizer test signal data pattern to the phase locked loop test signal data pattern is specified as a range of lines, rather than as a single specific line. Although the specific line selected within the specified range in not te

25、chnically significant, the transition point should be consistent from frame to frame and from field to field (in the case of interlaced signal formats). Page 2 of 4 pages - STD.SMPTE RP 178-ENGL 1998 8357qOL 0003003 T53 RP 198-1 998 Table 1 - SDI checkfield sample values qualizer test signal phase l

26、ocked oop test signal first line last line (range) ata values) 300hCb 198h Y 198h Y polarity :ont ro I wp, latavalue 300h Cr 19oh Y 50i59.94 Hz I920 x 1035 interlaced 41 (field 2) 303 (field 2) (field 1) (field 2) samples O . 3836 1 . 3837 2 . 3838 3 . 3839 (every other frame) line 41 sample 1 295-3

27、02 858-865 296-303 (field 1) 859-866 (field 2) 557 (field 1) 1120 (field 2) samples O . 3836 1 . 3837 2 . 3838 3 . 3839 Non-50 Hz I920 x 1080 interlaced 21 (field 1) 584 (field 2) (field 1) (field 2) camples O . 3836 1 . 3837 2 . 3838 3 . 3839 (every other frame) line 21 sample 1 287-293 850-856 288

28、-294 (field 1) (field 2) 560 (field 1) 1123 (field 2) samples O . 3836 1 . 3837 2 . 3838 3 . 3839 85 1 -857 81 (field 1) 706 (field 2) (field 1) (field 2) samples O . 3836 1 . 3837 2 . 3838 3 . 3839 every other frame) line 81 sample 1 347-504 972-979 348-505 (field 1) (field 2) 620 (field 1) 1245 (f

29、ield 2) samples O . 3836 1 . 3837 2 . 3838 3 . 3839 973-980 42 578-585 samples O . 3836 1 . 3837 2 . 3838 3 . 3839 every other frame) line 42 sample 1 579-586 1121 samples O . 3836 1 . 3837 2 . 3838 3 . 3839 50 Hz 1920 x 1080 xogressive 161 696-703 samples O . 3836 1 . 3837 2 . 3838 3 . 3839 every o

30、ther frame) line 161 sample 1 697-704 1245 samples O . 3836 1 . 3837 2 . 3838 3 . 3839 1280 x 720 xogressive 26 382-389 samples O . 2556 1 . 2557 2 . 2558 3 . 2559 every other frame) line 26 sample 1 383-390 745 samples O . 2556 1 . 2557 2 . 2558 3 . 2559 ) The ordering of data values for each of th

31、e pairs of sample values may be reversed. If the ordering of the samples is reversed from the ordering in this table, then the polarity control word value is (200h Y). (See 3.4.) active picture line of every other frame (see 3.3). within these ranges must be consistent across all fields (see clause

32、4). 2, The polarity change word is a substitution of the first active picture area Y sample, made in the first 3, A range of line numbers for transitioning between the two test patterns is provided. The transition point Page 3 of 4 pages RP 198-1 998 vertical blanking interval eav sav horizontal bla

33、nking interval first line of active picture 1st half of active field 300h, 198h for equalizer testing ) 2nd half of active field for phase locked loop testing ) last line of active picture Zooh, 11oh ) The ordering of data values for each of the pairs of sample values may be reversed (see 3.4). Figu

34、re 1 - Serial digital interface checkfield Annex A (informative) Bibliography ANSIISMPTE 274M-1995, Television - 1920 x 1080 Scanning and Interface ANSIISMPTE 292M-1996, Television - Bit-Serial Digital ITU-R BT.1120, Digital Interfaces for 1125/60/2:1 and Interface for High-Definition Television Sys

35、tems ANSI/SMPTE296M-l997, Television- 1280 x 720 Scanning, Analog and Digital Representation and Analog Interface 1250/50/2:1 HDTV Studio Signals ANSIISMPTE 295M-1997, Television - 1920 x 1080 Eguchi, Takeo. Pathological check codes for serial digital 50-Hz - Scanning and Interfaces SMPTE 260M-1992, Television - Digital Representation and Bit-Parallel Interface - 112960 High-Definition Production System systems. SMPTE Journal 101 (8): 553-558; August 1992 Page 4 of 4 pages