REG NASA-LLIS-1315-2002 Lessons Learned Increasing ESD Susceptibility of Integrated Circuits (2002).pdf

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1、Lessons Learned Entry: 1315Lesson Info:a71 Lesson Number: 1315a71 Lesson Date: 2002-11-01a71 Submitting Organization: JPLa71 Submitted by: R. Kemski/ D. OberhettingerSubject: Increasing ESD Susceptibility of Integrated Circuits (2002) Abstract: ESD susceptibility remains a pressing reliability issue

2、 in IC design due to the continually decreasing feature size and the increasing vulnerability to voltages that are much lower than human sensory perception thresholds.Characterize the expected ESD levels and the susceptibility of ICs in the specific circuit prior to use (e.g., Human Body Model, Mach

3、ine Model, and/or Charged Device Model). Base facility ESD control measures on the most ESD sensitive device to be protected. Description of Driving Event: Electrostatic discharge (ESD) susceptibility remains a pressing reliability issue in integrated circuit (IC) design. The continually decreasing

4、feature size associated with modern electronic devices now makes them increasingly prone to ESD induced damage during handling and use. To obtain greater processing speed and to pack more circuitry into small packages, average feature sizes for IC packages today are about half the size of those in 1

5、995, and they are expected to decrease by 50% again by 2007. As the size of features and the width of conductors shrink, the decreased spacing in the circuitry reduces electrical isolation. A discharge of only a few volts can produce enough heat to burn through microelectronic features on the order

6、of 0.1 micron.In addition to microcircuits, many discrete semiconductor devices (e.g., transistors, diodes) are vulnerable to voltages that are much lower than human sensory perception thresholds (3,000 volt static charge). The ESD control measures that are in general use by industry involve (1) pre

7、venting ESD from occurring by employing proper grounding and handling procedures during manufacturing and use, and (2) installing on-chip ESD protection circuitry. However, the effectiveness of ESD protection circuits also tends to decrease with decreasing device dimensions. Industry is employing Pr

8、ovided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-“ESD event modeling“ and associated physics-of-failure analyses during the design process for development of more robust ICs.References:1. “JPL Standard for Electrostatic Discharge (ESD) Control“ (D-1348)

9、, Rev. E, June 20, 2001.2. Lesson Learned No. 0297, “Integrated Circuit Damage due to Capacitor Residual Charge.“Additional Key Words: integrated circuit reliability, ESD sensitive devices, electrical overstress (EOS), EEE parts, electronics packaging, parts selection, approved parts list, fault pro

10、tection, ESD Control Plan, ESD requirementsLesson(s) Learned: As circuit dimensions continue to shrink and modern integrated circuits become more susceptible to ESD damage, circuit designs that minimize or eliminate ESD effects become increasingly important.Recommendation(s): 1. Characterize the exp

11、ected ESD levels and the susceptibility of ICs in the specific circuit prior to use. Determination of the potential ESD charge should be based on the Human Body Model (HBM), the Machine Model (MM), and/or Charged Device Model (CDM), as appropriate. Sensitivity of a device to ESD may be determined by

12、 experimentation, by use of the suppliers data, or by estimation based on comparison to devices of similar design (see Reference 1).2. All facility ESD control measures should be based on the most ESD sensitive device to be protected.Evidence of Recurrence Control Effectiveness: Corrective Action No

13、tice No. Z84172 was opened by JPL on June 23, 2004 to initiate and document appropriate Laboratory-wide corrective action on the above recommendations.Documents Related to Lesson: N/AMission Directorate(s): a71 Exploration SystemsProvided by IHSNot for ResaleNo reproduction or networking permitted w

14、ithout license from IHS-,-,-a71 Sciencea71 Space Operationsa71 Aeronautics ResearchAdditional Key Phrase(s): a71 Hardwarea71 Industrial Operationsa71 Packaging Handling Storagea71 Parts Materials & Processesa71 Payloadsa71 Safety & Mission AssuranceAdditional Info: Approval Info: a71 Approval Date: 2002-12-09a71 Approval Name: Carol Dumaina71 Approval Organization: JPLa71 Approval Phone Number: 818-354-8242Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-