1、JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONJESD209-2FJUNE 2012JEDECSTANDARDLow Power Double Data Rate 2(LPDDR2)(Revision of JESD209-2E, April 2011)SPECIAL DISCLAIMER: JEDEC has received information that certain patents or patent applications may be essential to this standard. However, as of the publica
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9、uments for alternative contact information.Published byJEDEC Solid State Technology Association 20133103 North 10th StreetSuite 240 SouthArlington, VA 22201-2107This document may be downloaded free of charge; however JEDEC retains thecopyright on this material. By downloading this file the individua
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11、3 North 10th Street, Suite 240 SouthArlington, Virginia 22201-2107or call (703) 907-7559or refer to www.jedec.org under Standards and Document/Copyright Information.Special Disclaimer JEDEC has received information that certain patents or patent applications may be essential to this standard. Howeve
12、r, as of the publication date of this standard, no statements regarding an assurance or refusal to license such patents or patent applications have been provided. Contact JEDEC for further information. JEDEC does not make any determination as to the validity or relevancy of such patents or patent ap
13、plications. Anyone making use of the standard assumes all liability resulting from such use. JEDEC disclaims any representation or warranty, express or implied, relating to the standard and its use.JEDEC Standard No. 209-2FContents-i-Scope. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14、 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Package ballout DQS1_t and DQS1_c to the data on DQ8 - DQ15.For x32 DQS0_t and DQS0_c correspond to the data on DQ0 - DQ7, DQS1_t and DQS1_c to the data on DQ8 - DQ15, DQS2_t and DQS2_c to the data on DQ16 - DQ23, DQ
15、S3_t and DQS3_c to the data on DQ24 - DQ31.DM0(x8)DM0-DM1(x16)DM0 - DM3 (x32)Input Input Data Mask: For LPDDR2 devices that do not support the DNV feature, DM is the input mask signal for write data. Input data is masked when DM is sampled HIGH coincident with that input data during a Write access.
16、DM is sampled on both edges of DQS_t. Although DM is for input only, the DM loading shall match the DQ and DQS_t (or DQS_c). DM0 is the input data mask signal for the data on DQ0-7.For x16 and x32 devices, DM1 is the input data mask signal for the data on DQ8-15.For x32 devices, DM2 is the input dat
17、a mask signal for the data on DQ16-23 and DM3 is the input data mask signal for the data on DQ24-31.JEDEC Standard No. 209-2FPage 14NOTE 1 Data includes DQ and DM.DM0/DNV0(x8)DM0/DNV0-DM1/DNV1(x16)DM0/DNV0 - DM3/DNV3 (x32)I/0 Input Data Mask/Data Not Valid: For LPDDR2 devices that support the DNV fe
18、ature, DM/DNV is bidirectional (used for write and read data). It is output with read data, input with write data. DM/DNV is the input mask signal for write data and is an output signal validating a read burst. For data write accesses:Input data is masked when DM/DNV is sampled HIGH coincident with
19、DQ input data during a WRITE access.DM0 is the input data mask signal for the data on DQ0-7.For x16 and x32 devices, DM1 is the input data mask signal for the data on DQ8-15.For x32 devices, DM2 is the input data mask signal for the data on DQ16-23 and DM3 is the input data mask signal for the data
20、on DQ24-31.For data read accesses:See 5.4.2 for detailed description of DNV functionality.DNV0, DNV1, DNV2, and DNV3 are driven coincident with output read data. DNV0, DNV1, DNV2, and DNV3 are driven with the same value and shall be sampled with DQS0, DQS1, DQS2, and DQS3 respectively.The DM/DNV loa
21、ding shall match the DQ and DQS_t (or DQS_c) loading. VDD1Supply Core Power Supply 1: Core power supply for LPDDR2-N and LPDDR2-SX devices.VDD2Supply Core Power Supply 2: Core power supply for LPDDR2-S2B, LPDDR2-S4 and LPDDR2-N-B devices. VDDCASupply Input Receiver Power Supply: Power supply for CA0
22、-9, CKE, CS_n, CK_t, and CK_c input buffers.VDDQSupply I/O Power Supply: Power supply for Data input/output buffers. VACCSupply NVM Acceleration Supply: NVM device specific embedded operation acceleration. VACCenables some NVM device specific functionality. When not used for NVM device specific func
23、tionality, VACC shall be driven to a level of VDD1.VREF(CA)Supply Reference Voltage for CA Command and Control Input Receiver: Reference voltage for all CA0-9, CKE, CS_n, CK_t, and CK_c input buffers.VREF(DQ)Supply Reference Voltage for DQ Input Receiver: Reference voltage for all Data input buffers
24、.VSSSupply GroundVSSCASupply Ground for Input ReceiversVSSQSupply I/O GroundZQ I/O Reference Pin for Output Drive Strength CalibrationName Type DescriptionJEDEC Standard No. 209-2FPage 152.13 LPDDR2 SDRAM AddressingTable 3 LPDDR2 SDRAM AddressingNOTE 1 The least-significant column address C0 is not
25、transmitted on the CA bus, and is implied to be zero.NOTE 2 tREFIvalues for all bank refresh is Tc = -2585 C, Tc means Operating Case TemperatureNOTE 3 Row and Column Address values on the CA bus that are not used are “dont care.”NOTE 4 No memory present at addresses with R13=R14=HIGH. ACT command w
26、ith R13=R14=HIGH is ignored (NOP). Write to R13=R14=HIGH is ignored (NOP). 2.14 LPDDR2 NVM Addressing2.14.1 Three-Phase AddressingThe memory controller delivers an array address to the memory in three phases (See Figure 1 and Figure 2). The Table 60 defines the required assignment of logical address
27、 bits to CA pins. Scrambling of the logical address bits in any order different than those described in the Command truth table is prohibited. During a Preactive command, part of a row address (driven on the CA input pins) is stored in a Row Address Buffer (RAB) selected by BA2-BA0. During an Activa
28、te command, BA2-BA0 select an RAB to retrieve the first part of the row address. Meanwhile, the remainder of the row address is driven on the CA input pins. These two parts of the row address select one row from the memory array. Activate also causes internal sensing circuits to transfer that memory
29、 content into a Row Data Buffer (RDB) also selected by BA2-BA0. An RAB, RDB pair selected by BA2-BA0 is referred to as a Row Buffer (RB). BA2-BA0 do not address any portion of the array and only select an RAB into which address is placed and/or an RDB into which data is placed. The controller may us
30、e any value of BA2-BA0 for any array location. During a Read or Write command BA2-BA0 selects an RDB, and the column address is driven on the CA input pins to choose the starting address of the read or write burst. The Preactive command is optional when the desired RAB already contains the desired p
31、artial row address. The Activate command is optional when the desired RDB already contains the desired memory content.Upon completion of Device Auto-Initialization, all Row Buffers are in the Idle state, and RABs contain 0x0000 and all RDBs contain indeterminate values.Items 64Mb 128Mb 256Mb 512Mb 1
32、Gb 2Gb 4Gb 6Gb 8GbDevice Type S2/S4 S2/S4 S2/S4 S2/S4 S2 S4 S2 S4 S2/S4 S2/S4 S2/S4Number of Banks 4 4 8 4 8 8Bank Addresses BA0-BA1 BA0-BA1 BA0-BA2 BA0-BA1 BA0-BA2 BA0-BA2tREFI(us)*215.6 15.6 7.8 7.8 7.8 7.8 3.9 3.9 3.9 3.9 3.9x8Row Addresses R0-R11 R0-R11 R0-R12 R0-R12 R0-R13 R0-R12 R0-R14 R0-R13
33、R0-R13R0-R14*4R0-R14Column Addresses*1C0-C8 C0-C9 C0-C9 C0-C10 C0-C10 C0-C10 C0-C10 C0-C10 C0-C11 C0-C11 C0-C11x16Row Addresses R0-R11 R0-R11 R0-R12 R0-R12 R0-R13 R0-R12 R0-R14 R0-R13 R0-R13R0-R14*4R0-R14Column Addresses*1C0-C7 C0-C8 C0-C8 C0-C9 C0-C9 C0-C9 C0-C9 C0-C9 C0-C10 C0-C10 C0-C10x32Row Add
34、resses R0-R11 R0-R11 R0-R12 R0-R12 R0-R13 R0-R12 R0-R14 R0-R13 R0-R13R0-R14*4R0-R14Column Addresses*1C0-C6 C0-C7 C0-C7 C0-C8 C0-C8 C0-C8 C0-C8 C0-C8 C0-C9 C0-C9 C0-C9JEDEC Standard No. 209-2FPage 162.5.1 Three-Phase Addressing (contd)NOTE 1 In the Preactive phase, amax is dependent on the density of
35、 the NVM device.NOTE 2 In the Activate phase, the lower order row address bit ax is dependent on the size of the Row Data Buffer (RDB).NOTE 3 In the Read phase, column address bit Cy is dependent on the size of the Row Data Buffer (RDB) and the data bus width.NOTE 4 An RAB, RDB pair selected by BA2:
36、0 is referred to as a Row Buffer (RB).NOTE 5 The least significant column address C0 is implied to be zero and is not transmitted on the CA bus.NOTE 6 An RAB, RDB pair can be associated with any portion of the memory array.amax:20Figure 1 LPDDR2-N: Three-Phase Address ReadNVMPreactive PhaseCy:1BA2:0
37、Memory ArrayRAB #0RAB #1RAB #2RAB #3RAB #7RDB #0RDB #1RDB #2RDB #3RDB #7Upper Row Address Lower Row Address Activate Phasea19:xOutputStateMachineDQRead PhaseBA2:0Row DecoderSense AmplifiersBA2:0JEDEC Standard No. 209-2FPage 172.5.1 Three-Phase Addressing (contd)NOTE 1 In the Preactive phase, amax is
38、 dependent on the density of the NVM device.NOTE 2 In the Activate phase, the lower order row address bit ax is dependent on the size of the Row Data Buffer (RDB).NOTE 3 In the Write phase, column address bit Cy is dependent on the size of the Row Data Buffer (RDB) and the data bus width.NOTE 4 An R
39、AB, RDB pair selected by BA2:0 is referred to as a Row Buffer (RB).NOTE 5 The least significant column address C0 is implied to be zero and is not transmitted on the CA bus.Table 4 64 Mb AddressingConfiguration 8 Mb x 8 4 Mb x 16 2 Mb x 32# of Row Buffers*2,3444Upper Row Address (PREACTIVE) a22-a20
40、a22-a20 a22-a20Lower Row Address (ACTIVE)*1a19-A5 a19-a5 a19-a5Column Address (READ/WRITE)*1,4a4-a1 (C4-C1) a4-a2 (C3-C1) a4-a3 (C2-C1)RDB size*132 Bytes 32 Bytes 32 BytesTable 5 128 Mb AddressingConfiguration 16 Mb x 8 8 Mb x 16 4 Mb x 32# of Row Buffers*2,3444Upper Row Address (PREACTIVE) a23-a20
41、a23-a20 a23-a20Lower Row Address (ACTIVE)*1a19-a5 a19-a5 a19-a5Column Address (READ/WRITE)*1,4a4-a1 (C4-C1) a4-a2 (C3-C1) a4-a3 (C2-C1)RDB size*132 Bytes 32 Bytes 32 Bytesamax:20Figure 2 LPDDR2-N: Three-Phase Address WriteNVMPreactive PhaseCy:1BA2:0Memory ArrayRAB #0RAB #1RAB #2RAB #3RAB #7RDB #0RDB
42、 #1RDB #2RDB #3RDB #7Upper Row Address Lower Row Address Activate Phasea19:xInputStateMachineDQWrite PhaseBA2:0Row DecoderSense AmplifiersBA2:0JEDEC Standard No. 209-2FPage 182.5.1 Three-Phase Addressing (contd)Table 6 256 Mb addressingConfiguration 32 Mb x 8 16 Mb x 16 8 Mb x 32# of Row Buffers*2,3
43、444Upper Row Address (PREACTIVE) a24-a20 a24-a20 a24-a20Lower Row Address (ACTIVE)*1a19-a5 a19-a5 a19-a5Column Address (READ/WRITE)*1,4a4-a1 (C4-C1) a4-a2 (C3-C1) a4-a3 (C2-C1)RDB size*132 Bytes 32 Bytes 32 BytesTable 7 512 Mb addressingConfiguration 64 Mb x 8 32 Mb x 16 16 Mb x 32# of Row Buffers*2
44、,3444Upper Row Address (PREACTIVE) a25-a20 a25-a20 a25-a20Lower Row Address (ACTIVE)*1a19-a5 a19-a5 a19-a5Column Address (READ/WRITE)*1,4a4-a1 (C4-C1) a4-a2 (C3-C1) a4-a3 (C2-C1)RDB size *132 Bytes 32 Bytes 32 BytesTable 8 1 Gb addressingConfiguration 128 Mb x 8 64 Mb x 16 32 Mb x 32# of Row Buffers
45、*2,3444Upper Row Address (PREACTIVE) a26-a20 a26-a20 a26-a20Lower Row Address (ACTIVE)*1a19-a5 a19-a5 a19-a5Column Address (READ/WRITE)*1,4a4-a1 (C4-C1) a4-a2 (C3-C1) a4-a3 (C2-C1)RDB size *132 Bytes 32 Bytes 32 BytesTable 9 2 Gb addressingConfiguration 256 Mb x 8 128 Mb x 16 64 Mb x 32# of Row Buff
46、ers*2,3444Upper Row Address (PREACTIVE) a27-a20 a27-a20 a27-a20Lower Row Address (ACTIVE)*1a19-a5 a19-a5 a19-a5Column Address (READ/WRITE)*1,4a4-a1 (C4-C1) a4-a2 (C3-C1) a4-a3 (C2-C1)RDB size *132 Bytes 32 Bytes 32 BytesTable 10 4 Gb addressingConfiguration 512 Mb x 8 256 Mb x 16 128 Mb x 32# of Row
47、 Buffers*2,3444Upper Row Address (PREACTIVE) a28-a20 a28-a20 a28-a20Lower Row Address (ACTIVE)*1a19-a5 a19-a5 a19-a5Column Address (READ/WRITE)*1,4a4-a1 (C4-C1) a4-a2 (C3-C1) a4-a3 (C2-C1)RDB size *132 Bytes 32 Bytes 32 BytesJEDEC Standard No. 209-2FPage 192.5.1 Three-Phase Addressing (contd)Notes f
48、or Tables 4-13NOTE 1 All tables above show examples using minimum 32 Byte RDB Size, see Table 14 for other RDB sizes.NOTE 2 The number of Row Buffers can be 4 or 8. A controller may use a smaller number of Row Buffers provided that the appropriate most significant BA addresses are driven to “0”.NOTE
49、 3 One Row Buffer consists of a pair of one Row Address Buffer (RAB) and one Row Data Buffer (RDB), selected by Buffer Address, BA0-BA2 (CA7r-CA9r).NOTE 4 The least significant column address C0 is implied to be zero and is not transmitted on the CA bus. NOTE 5 Row and Column Address values on the CA bus that are not used are “dont care.”Table 11 8 Gb addressingConfiguration 1 Gb x 8 512 Mb x 16 256 Mb x 32# of Row Buffers*2,3444Upper Row Address (PREACTIVE) a29-a20 a29-a20 a29-a20Lower Row Address (ACTIVE)*1a19-
