1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/A PREPARED BY RICK OFFICER DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil/ Original
2、 date of drawing YY-MM-DD CHECKED BY RAJESH PITHADIA TITLE MICROCIRCUIT, DIGITAL-LINEAR, CURRENT OUTPUT/SERIAL INPUT, 16 BIT, DIGITAL TO ANALOG CONVERTER, MONOLITHIC SILICON 13-06-19 APPROVED BY CHARLES F. SAFFLE SIZE A CODE IDENT. NO. 16236 DWG NO. V62/12662 REV PAGE 1 OF 12 AMSC N/A 5962-V003-13 P
3、rovided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12662 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance current output/seri
4、al input, 16 bit, digital to analog converter (DAC) microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for
5、 identifying the item on the engineering documentation: V62/12662 - 01 X B Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 1/ AD5543 Current output/serial input, 16 bit, digital to analog converter
6、1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 8 MO-187-AA Small outline package 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designa
7、tor Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other _ 1/ The device contains 1040 transistors. The die size measures 55 mil x 73 mil or 4,015 square mil. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,
8、-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12662 REV PAGE 3 1.3 Absolute maximum ratings. 2/ Positive supply power input (VDD) to analog and digital ground (GND) . -0.3 V to +8 V DAC reference input (VREF) to GND -18 V to +18 V Logic inputs to GND . -0.3 V to +8
9、V Voltage at DAC current output (V(IOUTx) to GND . -0.3 V, VDD+ 0.3 V Input current to any pin except supplies . 50 mA Power dissipation (PD) . (TJmax TA) / JAand see table I. Maximum junction temperature range (TJ) . 150C Storage temperature range (TSTG) -65C to +150C Lead temperature: Vapor phase,
10、 60 seconds 215C Infrared, 15 seconds 220C 1.4 Recommended operating conditions. 3/ Supply voltage range (VDD) . 5 V Operating free-air temperature range (TA) . -55C to +125C 1.5 Thermal characteristics. Thermal resistance, junction to ambient (JA) 150C/W 2/ Stresses beyond those listed under “absol
11、ute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for exten
12、ded periods may affect device reliability. 3/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. Provided by IHSNot for Resale
13、No reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12662 REV PAGE 4 2. APPLICABLE DOCUMENTS JEDEC Solid State Technology Association JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices
14、(Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein a
15、nd as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recom
16、mended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline sha
17、ll be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Timing waveforms. The timing waveforms shall be as shown in figure 3. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA
18、LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12662 REV PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions 2/Temperature, TADevice type Limits Unit Min Max Static performance 3/ Resolution N 1 LSB = VREF/ 216= 153 V when VREF= 10 V -55C to +1
19、25C 01 16 Bits Relative accuracy INL -55C to +125C 01 3 LSB Differential nonlinearity DNL Monotonic -55C to +125C 01 -1/+2 LSB Output leakage current IOUTData = 0x0000 +25C 01 10 nA +125C 20 Full scale gain error GFSEData = 0xFFFF +25C 01 1/4 typical maximum mV Full scale temperature coefficient TCV
20、FS4/ +25C 01 1 typical ppm/ C Reference input VREF range VREF-55C to +125C 01 -15 +15 V Input resistance RREF+25C 01 5 typical k 5/ Input capacitance 4/ CREF+25C 01 5 typical pF Analog output Output current IOUTData = 0xFFFF +25C 01 2 typical mA Output capacitance 4/ COUTCode dependent +25C 01 200 t
21、ypical pF Logic inputs and output Logic input low voltage VIL-55C to +125C 01 0.8 V Logic input high voltage VIH-55C to +125C 01 2.4 V Input leakage current IIL-55C to +125C 01 10 A Input capacitance 4/ CIL-55C to +125C 01 10 pF See footnotes at end of table. Provided by IHSNot for ResaleNo reproduc
22、tion or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12662 REV PAGE 6 TABLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions 2/Temperature, TADevice type Limits Unit Min Max Interface timi
23、ng 4/ 6/ Clock input frequency fCLK-55C to +125C 01 50 MHz Clock width high tCH-55C to +125C 01 10 ns Clock width low tCL-55C to +125C 01 10 ns CS to clock setup tCSS-55C to +125C 01 0 ns Clock to CS hold tCSH-55C to +125C 01 10 ns Data setup tDS-55C to +125C 01 5 ns Data hold tDH-55C to +125C 01 10
24、 ns Supply characteristics Power supply range VDD RANGE-55C to +125C 01 4.5 5.5 V Positive supply current IDDLogic inputs = 0 V -55C to +125C 01 10 A Power dissipation PD Logic inputs = 0 V -55C to +125C 01 0.055 mW Power supply sensitivity PSS VDD= 5% -55C to +125C 01 0.006 %/% AC characteristics 6
25、/ Output voltage settling time tSTo 0.1% of full scale, data = 0x0000 to 0xFFFF to 0x0000 +25C 01 0.5 typical s Reference multiplying bandwidth BW VREF= 100 mV rms, data = 0xFFFF +25C 01 6.6 typical MHz DAC glitch impulse Q VREF= 0 V, data = 0x7FFF to 0x8000 -55C to +125C 01 7 nV-sec Feedthrough err
26、or VOUT/ VREFData = 0x0000, VREF = 10 mV rms, same channel -55C to +125C 01 -83 dB See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12662 REV P
27、AGE 7 TABLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions 2/Temperature, TADevice type Limits Unit Min Max AC characteristics 6/ Digital feedthrough Q CS= 1 and fCLK= 1 MHz -55C to +125C 01 7 nV-sec Total harmonic distortion THD VREF= 5 Vpp, data = 0xFFFF, f = 1 kHz
28、+25C 01 -103 typical dB Output spot noise voltage eNf = 1 kHz, BW = 1 Hz -55C to +125C 01 12 nV / Hz1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across
29、 the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ Unless otherwise specified, VDD= 5 V 10%, VSS= 0 V, IOUT= virtual GND, GND = 0 V, VREF= 10 V, and TA= full
30、 temperature range. 3/ All static performance tests (except IOUT) are performed in a closed loop system using an external precision OP177 current to voltage amplifier. The RFBterminal is tied to the amplifier output. The +INPUT operational amplifier is grounded, and the DAC IOUTis tied to the INPUT
31、operational amplifier. Typical values represent average readings measured at 25C. 4/ These parameters are guaranteed by design and are not subject to production testing. 5/ All ac characteristic tests are performed in a closed loop system using an AD8038 current to voltage (I to V) converter amplifi
32、er except for total harmonic distortion (THD) where an AD8065 was used. 6/ All input control signals are specified with tR= tF= 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LA
33、ND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12662 REV PAGE 8 Case X FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12662
34、REV PAGE 9 Case X Symbol Dimensions Inches Millimeters Min Med Max Min Med Max A - - .043 - - 1.10 A1 .029 .033 .037 0.75 0.85 0.95 A2 .001 0.10 coplanarity .005 0.05 0.10 coplanarity 0.15 b .009 - .015 0.25 - 0.40 c .003 - .009 0.09 - 0.23 D .110 .118 .125 2.80 3.00 3.20 E .110 .118 .125 2.80 3.00
35、3.20 E1 .183 .192 .202 4.65 4.90 5.15 e .025 BSC 0.65 BSC L .015 .021 .031 0.40 0.55 0.80 NOTES: 1. Controlling dimensions are millimeter, inch dimensions are given for reference only. 2. Falls within reference to JEDEC MO-187-AA. FIGURE 1. Case outline - Continued. Provided by IHSNot for ResaleNo r
36、eproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12662 REV PAGE 10 Device type 01 Case outline X Terminal number Terminal symbol Description 1 CLK Clock input. Positive edge triggered, clocks data into shift
37、 register. 2 SDI Serial register input. Data loads directly into the shift register MSB first. Extra leading bits are ignored. 3 RFBInternal matching feedback resistor. This pin connects to an external operational amplifier for voltage output. 4 VREFDAC reference input pin. Establishes DAC full scal
38、e voltage. Constant input resistance versus code. 5 IOUTDAC current output. This pin connects to the inverting terminal of the external precision current to voltage operational amplifier for voltage output. 6 GND Analog and digital ground. 7 VDDPositive power supply input. Specified range of operati
39、on at 5 V 10%. 8 CS Chip select. Active low digital input. Transfers shift register data to DAC register on rising edge. FIGURE 2. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE
40、IDENT NO. 16236 DWG NO. V62/12662 REV PAGE 11 FIGURE 3. Timing waveforms. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12662 REV PAGE 12 4. VERIFICATION 4.1 Product assur
41、ance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive device
42、s, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturers standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and
43、are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturers data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided
44、. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all current sources of supply at http:/
45、www.landandmaritime.dla.mil/Programs/Smcr/. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Vendor part number 2/ V62/12662-01XB 24355 AD5543SRMZ-EP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering
46、documentation. 2/ Z = RoHS complaint part. CAGE code Source of supply 24355 Analog Devices Route 1 Industrial Park P.O. Box 9106 Norwood, MA 02062 Point of contact: Raheen Business Park Limerick, Ireland Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-
